CLC5903SM/NOPB National Semiconductor, CLC5903SM/NOPB Datasheet - Page 19

• Manufacturer Part Number: CLC5903SM/NOPB
• Description: IC DGTL TUNER/AGC DUAL 128-FBGA
• Manufacturer: National Semiconductor
• Type: Tunerr

Specifications of CLC5903SM/NOPB

• Applications: Base Stations
• Mounting Type: Surface Mount
• Package / Case: 128-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *CLC5903SM; *CLC5903SM/NOPB; CLC5903SM

chip sends the I data first by setting SFS high (or low if
SFS_POL in the input control register is set high) for one
clock cycle, and then transmitting the data, MSB first, on as
many SCK cycles as are necessary. Without a pause, the Q
data is transferred next as shown in Figure 30(a). If the
PACKED control bit is high, then the I and Q components are
sent as a double length word with only one SFS strobe as
shown in Figure 30(b). If both channels are multiplexed out
the same serial pin, then the subsequent I/Q channel words
will be transmitted immediately following the first I/Q pair as
shown in Figure 30(c). Figure 30(c) also shows how
SFS_MODE=1 allows the SFS signal to be used to identify
the I and Q channels in the TDM serial transmission. The
serial output rate is programmed by the RATE register to CK
divided by 1, 2, 4, 8, 16, or 32. The serial interface will not
work properly if the programmed rate of SCK is insufficient to
clock out all the bits in one OSP.
Serial Port Daisy-Chain Mode
Two CLC5903s can be connected in series so that a single
DSP serial port can receive four DDC output channels. This
mode is enabled by setting the SDC_EN bit to ‘1’ on the
serial daisy-chan (SDC) master. The SDC master is the
CLC5903 which is connected to the DSP while the SDC
slave’s serial output drives the master. The SDC master’s
RATE register must be set so that its SCK rate is twice that of
the SDC slave, the SDC master must have MUX_MODE=1,
the SDC slave must have MUX_MODE=0 and PACKED=1,
and both chips must come out of a MR or SI event within four
CK periods of each other. In this configuration, the master’s
serial output data is shifted out to the DSP then the slave’s
serial data is shifted out. All the serial output data will be
muxed onto the master’s AOUT pin as shown in Figure 31.
Serial Port Output Number Formats
Several numeric formats are selectable using the FORMAT
control register. The I/Q samples can be rounded to 16 or 24
bits, or truncated to 8 bits. The packed mode works as
described above for these fixed point formats. A floating point
format with 138dB of dynamic range in 12 bits is also pro-
vided. The mantissa (m) is 8 bits and the exponent (e) is 4
bits. The MSB of each segment is transmitted first. When this
mode is selected, the I/Q samples are packed regardless of
the state of MUX_MODE, and the data is sent as mI/eI/eQ/
mQ which allows the two exponents to form an 8-bit word.
This is shown in Figure 30(d). For all formats, once the
defined length of the word is complete, SCK stops toggling.
AGC
(Continued)
CLC5903
SDC_EN=0
MUX_MODE=0
PACKED=1
ADCs and
Slave
DVGAs
AOUT
BOUT
SCK
SFS
SCK
Figure 31. Serial Daisy-Chain Mode
MASTER
=2*SCK
19
SLAVE
POUT_SEL[0]
POUT_SEL[1]
POUT_SEL[2]
SCK_IN
Parallel Outputs
Output data from the channels can also be taken from a
1 6 - b i t p a r a l l e l p o r t . A 3 - b i t w o r d a p p l i e d t o t h e
POUT_SEL[2:0] pins determines which 16-bit segment is
multiplexed to the parallel port. Table 2 defines this mapping.
To allow for bussing of multiple chips, the parallel port is
tri-stated unless POUT_EN is low. The RDY signal indicates
the start of an OSP and that new data is ready at the parallel
output. The user has one OSP to cycle through whichever
registers are needed. The RATE register must be set so that
each OSP is at least 5 SCK periods.
Parallel Port Output Numeric Formats
The I/Q samples can be rounded to 16 or 24 bits or the full
32 bit word can be read. By setting the word size to 32 bits it
is possible to read out the top 16 bits and only observe the
top 8 bits if desired. Additionally, the output samples can be
formatted as floating point numbers with an 8-bit mantissa
and a 4 bit exponent. For the fixed-point formats, the valid
bits are justified into the MSBs of the registers of Table 2 and
all other bits are set to zero. For the floating point format, the
valid bits are placed in the upper 16 bits of the appropriate
channel register using the format 0000/eI/mI for the I sam-
ples.
AGC
The CLC5903 AGC processor monitors the output level of
the ADC and servos it to the desired setpoint. The ADC input
is controlled by the DVGA to maintain the proper setpoint
POUT_SEL
Table 2. Register Selection for Parallel Output
0
1
2
3
4
5
6
7
CLC5903
SDC_EN=1
MUX_MODE=0
Master
ADCs and
DVGAs
IA upper 16 bits
IA lower 16 bits
QA upper 16 bits
QA lower 16 bits
IB upper 16 bits
IB lower 16 bits
QB upper 16 bits
QB lower 16 bits
Normal Register
Contents
AOUT
SCK
SFS
RDY
ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
0000/eIA/mIA
0x0000
0000/eQA/mQA
0x0000
0000/eIB/mIB
0x0000
0000/eQB/mQB
0x0000
Register Contents
To DSP
Floating Point
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