CLC5903SM/NOPB National Semiconductor, CLC5903SM/NOPB Datasheet - Page 24

• Manufacturer Part Number: CLC5903SM/NOPB
• Description: IC DGTL TUNER/AGC DUAL 128-FBGA
• Manufacturer: National Semiconductor
• Type: Tunerr

Specifications of CLC5903SM/NOPB

• Applications: Base Stations
• Mounting Type: Surface Mount
• Package / Case: 128-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *CLC5903SM; *CLC5903SM/NOPB; CLC5903SM

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AGC Theory of Operation
A block diagram of the AGC is shown in Figure 34. The
DVGA interface comprises four pins for each of the channels.
The first three pins of this interface are a 3-bit binary word
that controls the DVGA gain in 6dB steps (AGAIN). The final
pin is ASTROBE which allows the AGAIN bits to be latched
into the DVGA’s register. A key feature of the ASTROBE,
illustrated Figure 35, is that it toggles only if the data on
AGAIN has changed from the previous cycle. Not shown is
that ASTROBE and BSTROBE are independent. For exam-
ple, ASTROBE only toggles when AGAIN has changed.
BSTROBE will not toggle because AGAIN has changed.
This is done to minimize unnecessary digital noise on the
sensitive analog path through the DVGA. ASTROBE and
BSTROBE are asserted during MR and SI to properly initial-
ize the DVGAs.
The absolute value circuit and the 2-stage, decimate-by-8
CIC filter comprise the power detection part of the AGC. The
power detector bandwidth is set by the CIC filter to F
The absolute value circuit doubles the effective input fre-
quency. This has the effect of reducing the power detector
bandwidth from F
For a full-scale sinusoidal input, the absolute value circuit
output is a dc value of
value circuit also generates undesired even harmonic terms,
the CIC filter (response shown in Figure 36), is required to,
remove these harmonics. The first response null occurs at
F
magnitude is at least 25dB below the dc value from F
9F
AGC Theory of Operation
(from MUXA)
CK
AIN[13:4]
CK
/8, where F
Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information.
AGAIN[2:0]
/10. Because the 2
ASTROBE
CK/8
CK
LOG
FUNCTION PROGRAMMED
CK
CK
is the clock frequency, and the response
INTO RAM
/8 to F
-REF
10
nd
511
CK
harmonic from the absolute value
/16.
2
16
. Because the absolute
Figure 34. CLC5903 AGC circuit, Channel A
(Continued)
9
P
CK
OUT
9
/10 to
CK
AGC_HOLD_IC
/8.
24
AGC_TABLE
5
circuit is about 10dB below the dc this means that the ripple
in the detected level is about 0.7dB or less for input frequen-
c i e s b e t w e e n F
AGC_COMB_ORD register to either 1 or 2 will narrow the
power detector’s bandwidth as shown in Figure 36.
The “FIXED TO FLOAT CONVERTER” takes the fixed point
9-bit output from the CIC filter and converts it to a “floating
point” number. This conversion is done so that the 32 values
in the RAM can be uniformly assigned (dB scale) to detected
power levels (54 dB range). This provides a resolution of
1.7dB between detected power levels. The truth table for this
converter is given in Table 3. The upper three bits of the out-
put represent the exponent (e) and the lower 2 are the man-
tissa (m). The exponent is determined by the position of the
ASTROBE does not pulse because AGAIN[2:0] does not change
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
Figure 36. Power detector filter response, 52MHz
10
0
0
8
AGC_LOOP_GAIN
5
AGC_COMB_ORD=2
AGC Power Detection Filter: Amplitude Response
10
12
C K
15
AGC_COMB_ORD=0
AGC_COMB_ORD=1
/ 2 0 t o 1 9 F
20
Frequency/MHz
12
25
30
C K
35
/ 2 0 . S e t t i n g t h e
CIC
CIC + 1−tap Comb
CIC + 4−tap Comb
AGC_IC_A
40
3
45
AGAIN
EXP
50