STA30613TR STMicroelectronics, STA30613TR Datasheet - Page 23

• Manufacturer Part Number: STA30613TR
• Description: IC PROCESSOR AUD DGTL DDX 64TQFP
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Processorr

Specifications of STA30613TR

• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 497-3945-2

Basic Limiter and Volume Flow Diagram.
A limiter is basically a variable gain device, where the amount of gain applied depends on the input signal level.
As the name implies, compression limits the dynamic range of the signal.
The STA306 includes 2 independent limiter blocks.
The purpose of the limiters is to automatically reduce the dynamic range of the input signal to prevent the out-
puts from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environ-
ment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the
DRC bit in Configuration Register B; address 0x02, bit 7.
Each channel can be mapped to either limiter or not mapped. Non-mapped channels will clip when 0dBFS is
exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum
absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the
gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to
set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain
can be added digitally within the STA306 it is possible to exceed 0dBFS or any other LxAT setting. When this
occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced
when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The
gain reduction occurs on a peak-detect algorithm.
The release of limiter (uncompression), when the gain is again increased, is dependent on a RMS-detect algo-
rithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared
to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below
the release threshold, the gain is again increased (uncompressed) at a rate dependent upon the Release Rate
register. The gain can never be increased past its set value and therefore the release will only occur if the limiter
has already reduced the gain.
The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as
over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In
AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is
set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is
set relative to the maximum volume setting plus the attack threshold.
Table 7. Channel Limiter Mapping as a function of CxLS bits.
Gain/Volume
Input
CxLS(1,0)
00
01
10
Gain
Attenuation
Limiter
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
Channel Limiter Mapping
Saturation
RMS
Output
STA306
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