STM8S105S4 STMicroelectronics, STM8S105S4 Datasheet - Page 119

• Manufacturer Part Number: STM8S105S4
• Description: Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM
• Manufacturer: STMicroelectronics

Specifications of STM8S105S4

• Ram: Up to 2 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
• Two Watchdog Timers: Window watchdog and independent watchdog

STM8S105xx
OPT3 watchdog
OPT4 wakeup
AFR5
(check only one option)
AFR6
(check only one option)
AFR7
(check only one option)
WWDG_HALT
(check only one option)
WWDG_HW
(check only one option)
IWDG_HW
(check only one option)
LSI_EN
(check only one option)
HSITRIM
(check only one option)
PRSC
(check only one option)
CKAWUSEL
(check only one option)
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port D4 alternate function = BEEP.
DocID14771 Rev 10
[ ] for 16 MHz to 128 kHz prescaler.
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
[ ] 0: LSI clock source selected for AWU.
[ ] 1: HSE clock with prescaler selected as clock source
for AWU.
[ ] 0: No reset generated on halt if WWDG active.
[ ] 1: Reset generated on halt if WWDG active.
[ ] 0: WWDG activated by software.
[ ] 1: WWDG activated by hardware.
[ ] 0: IWDG activated by software.
[ ] 1: IWDG activated by hardware.
[ ] 0: LSI clock is not available as CPU clock source.
[ ] 1: LSI clock is available as CPU clock source.
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
Ordering information
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