STM8S105S4 STMicroelectronics, STM8S105S4 Datasheet - Page 14

no-image

STM8S105S4

Manufacturer Part Number
STM8S105S4
Description
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S105S4

Ram
Up to 2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
Two Watchdog Timers
Window watchdog and independent watchdog

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM8S105S4
Manufacturer:
ST
0
Part Number:
STM8S105S4T3C
Manufacturer:
ST
0
Part Number:
STM8S105S4T6
Manufacturer:
ST
0
Part Number:
STM8S105S4T6
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8S105S4T6
0
Part Number:
STM8S105S4T6C
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8S105S4T6C
Manufacturer:
ST
0
Part Number:
STM8S105S4T6C
Manufacturer:
STM
Quantity:
200
Part Number:
STM8S105S4T6C
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8S105S4T6C
Manufacturer:
ST
Quantity:
18 870
Part Number:
STM8S105S4T6C
0
Part Number:
STM8S105S4T6CTR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8S105S4T6CTR
0
Company:
Part Number:
STM8S105S4T6CTR
Quantity:
15 000
Product overview
4.5
14/127
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
-
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
Medium density
Flash program memory
  (up to 32 Kbytes)
Data
EEPROM
memory
Figure 2: Flash memory organisation
DocID14771 Rev 10
Remains write protected during IAP
Write access possible for IAP
Data memory area ( 1 Kbyte)
Program memory area
Option bytes
UBC area
MASTER
) coming from different oscillators
(2 first pages) up to
Programmable area
from 1 Kbyte
32 Kbytes
(1 page steps)
STM8S105xx

Related parts for STM8S105S4