STM8TL53C4 STMicroelectronics, STM8TL53C4 Datasheet
STM8TL53C4
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STM8TL53C4 Summary of contents
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... USART with fractional baud rate generator ■ Development support – Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging – In-circuit emulation (ICE) ■ 96-bit unique ID Doc ID 022344 Rev 1 STM8TL53C4 STM8TL53G4 Preliminary data 1/62 www.st.com 1 ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8TL53xx 8 Unique ...
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... List of tables List of tables Table 1. Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Legends/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. STM8TL53C4/G4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. Unique ID registers (96 bits Table 11 ...
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... STM8TL53xx List of figures Figure 1. STM8TL53C4/G4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Standard 48-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. Standard 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 8. Power supply scheme Figure 9. ...
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... Flash memory related information. For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). All devices of the STM8TL53C4/G4 product line provide the following benefits: ● Advanced capacitive sensing – ...
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... STM8TL53C4/G4 microcontrollers feature low power low-voltage single-supply program Flash memory. The STM8TL53C4/G4 are based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools ...
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... Product overview 3 Product overview Figure 1. STM8TL53C4/G4 block diagram 16 MHz internal 38 kHz internal PXS_VREG PXS_RX(0a..9a, 0b..9b) PXS_TX(0..14) PXS_RFIN PXS_TRIG SCL, SDA MOSI, MISO, SCK, NSS RX, TX, CK Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator I²C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset ...
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... The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real- time by means of shadow registers. 3.4 Interrupt controller The STM8TL53C4/G4 features a nested vectored interrupt controller: ● Nested interrupts with 3 software priority levels ● 22 interrupt vectors with hardware priority ● ...
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... The ProxSense acquisition can be operated in Run, Wait and Active-halt modes. 3.7 Voltage regulators The STM8TL53C4/G4 devices embed an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals and a second internal voltage regulator providing a stable power supply (around 1.45V) for the ProxSense peripheral. ...
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... STM8TL53xx 3.8 Clock control The STM8TL53C4/G4 embed a robust clock controller used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. ...
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... Product overview 3.13 Beeper STM8TL53C4/G4 devices include a beeper function used to generate a beep signal in the range kHz when the LSI clock is operating at a frequency of 38 kHz. 3.14 USART The universal synchronous receiver/transmitter interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format ...
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STM8TL53xx 3.18 TouchSensing dedicated library available upon request ● Complete C source code library with firmware examples (MISRA compliant) ● Multifunction capability to combine capacitive sensing functions with traditional MCU features ● Flexible touchkey / wheel / slider / proximity ...
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Pin description 4 Pin description Figure 2. Standard 48-pin UFQFPN package pinout 1. HS corresponds high sink/source capability. 2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply ...
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STM8TL53xx Figure 3. Standard 28-pin UFQFPN package pinout ] 1. HS corresponds high sink/source capability. 2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in ...
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... Pin description Table 2. Legends/abbreviations Type Level Port and control configuration Reset state Table 3. STM8TL53C4/G4 pin description Pin no. Pin name 1 PB6/ PXS_TX14 I/O (1) PA0 /SWIM I/O BEEP PA1/SPI_NSS I/O [TIM3_CH1] PA2/SPI_SCK USART_CK/ I/O (2) [TIM3_CH2] PA3/SPI_MISO USART_TX/ I/O (2) I2C_SDA PA4/SPI_MOSI USART_RX/ I/O I2C_SCL 7 4 VDD ...
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... STM8TL53xx Table 3. STM8TL53C4/G4 pin description (continued) Pin no. Pin name 9 6 PXS_VREG S ( PA5/NRST I/O PA6/ PXS_TRIG I/O CLK_CCO 12 9 PA7/PXS_RFIN I PXS_RX0a 14 PXS_RX0b 15 11 PXS_RX1a 16 PXS_RX1b 17 12 PXS_RX2a 18 PXS_RX2b 19 13 PXS_RX3a 20 PXS_RX3b 21 14 PXS_RX4a 22 PXS_RX4b 23 15 PXS_RX5a 24 PXS_RX5b 25 16 PXS_RX6a Input ...
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... Pin description Table 3. STM8TL53C4/G4 pin description (continued) Pin no. Pin name 26 PXS_RX6b 27 17 PXS_RX7a 28 PXS_RX7b 29 PXS_RX8a 30 PXS_RX8b 31 PXS_RX9a 32 PXS_RX9b 33 18 PD0/PXS_TX0 I PD1/PXS_TX1 I PD2/PXS_TX2 I PD3/PXS_TX3 I/O 37 VSSIO S 38 VDDIO S PD4/PXS_TX4 I/O TIM2_CH1 PD5/PXS_TX5 I/O TIM2_CH2 PD6/PXS_TX6 I/O TIM3_CH1 18/62 Input Output ...
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... STM8TL53xx Table 3. STM8TL53C4/G4 pin description (continued) Pin no. Pin name PD7/PXS_TX7 I/O TIM3_CH2 PB0/PXS_TX8 I/O TIM3_ETR (2) PB1 /PXS_TX9 44 I/O / TIM2_ETR 45 PB2/PXS_TX10 I/O 46 PB3/PXS_TX11 I/O 47 PB4/PXS_TX12 I/O 48 PB5/PXS_TX13 I/O 1. The PA0/SWIM pin is in input pull-up during the reset phase and after reset release pull-up is applied to PA2, PA3 and PB1 during the reset phase. These three pins are input floating after reset release. ...
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Memory and register map 5 Memory and register map Figure 4. Memory map 1. Refer to Table 5 for an overview of hardware register mapping, to registers, and to Table 6 20/62 0x00 0000 RAM (4 Kbytes) including Stack 0x00 ...
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STM8TL53xx Figure 5. Flash and RAM boundary addresses Memory area RAM Flash program memory Table 4. I/O Port hardware register map Address Block 0x00 5000 0x00 5001 0x00 5002 Port A 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 ...
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Memory and register map Table 5. General hardware register map Address Block Register label 0x00 5050 FLASH_CR1 0x00 5051 FLASH_CR2 0x00 5052 Flash FLASH _PUKR 0x00 5053 FLASH _DUKR 0x00 5054 FLASH _IAPSR 0x00 5055 to 0x00 509F 0x00 50A0 ...
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STM8TL53xx Table 5. General hardware register map (continued) Address Block Register label 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP 0x00 50F4 to 0x00 51FF 0x00 5200 0x00 5201 0x00 5202 SPI 0x00 ...
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Memory and register map Table 5. General hardware register map (continued) Address Block Register label 0x00 5230 0x00 5231 0x00 5232 USART_BRR1 0x00 5233 USART_BRR2 USART 0x00 5234 USART_CR1 0x00 5235 USART_CR2 0x00 5236 USART_CR3 0x00 5237 USART_CR4 0x00 5238 ...
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STM8TL53xx Table 5. General hardware register map (continued) Address Block Register label 0x00 5280 0x00 5281 0x00 5282 TIM3_SMCR 0x00 5283 0x00 5284 0x00 5285 0x00 5286 0x00 5287 0x00 5288 TIM3_CCMR1 0x00 5289 TIM3_CCMR2 0x00 528A TIM3_CCER1 TIM3 0x00 ...
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Memory and register map Table 5. General hardware register map (continued) Address Block Register label 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 PXS 0x00 5305 0x00 5306 PXS_CKCR1 0x00 5307 PXS_CKCR2 0x00 5308 PXS_RXENRH 0x00 5309 PXS_RXENRL ...
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STM8TL53xx Table 5. General hardware register map (continued) Address Block Register label 0x00 5325 PXS_RX2CNTRL 0x00 5326 PXS_RX3CNTRH 0x00 5327 PXS_RX3CNTRL 0x00 5328 PXS_RX4CNTRH 0x00 5329 PXS_RX4CNTRL 0x00 532A PXS_RX5CNTRH 0x00 532B PXS_RX5CNTRL 0x00 532C PXS PXS_RX6CNTRH 0x00 532D PXS_RX6CNTRL ...
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Memory and register map Table 5. General hardware register map (continued) Address Block Register label 0x00 5350 PXS_RX0EPCCSELR 0x00 5351 PXS_RX1EPCCSELR 0x00 5352 PXS_RX2EPCCSELR 0x00 5353 PXS_RX3EPCCSELR 0x00 5354 PXS_RX4EPCCSELR PXS 0x00 5355 PXS_RX5EPCCSELR 0x00 5356 PXS_RX6EPCCSELR 0x00 5357 PXS_RX7EPCCSELR ...
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STM8TL53xx Table 6. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 0x00 7F60 CFG 0x00 7F61 0x00 7F6F 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 ITC-SPR 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 0x00 ...
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Interrupt vector mapping 6 Interrupt vector mapping Table 7. Interrupt mapping IRQ Source Description No. block RESET Reset TRAP Software interrupt 0 FLASH end of programing/ 1 FLASH write attempted to protected page interrupt End of conversion/First 2 PXS conversion ...
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STM8TL53xx Table 7. Interrupt mapping (continued) IRQ Source Description No. block TIM3 update/overflow/ 21 TIM3 trigger/break interrupt TIM3 capture/compare 22 TIM3 interrupt 23- 24 TIM4 update/overflow/ 25 TIM4 trigger interrupt SPI1 TX buffer empty/ 26 SPI1 RX buffer not empty/ ...
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Option bytes 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ...
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STM8TL53xx Table 9. Option byte description (continued) OPT4 Caution: After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. WWDG_HALT: Window watchdog reset on Halt/Active-halt 0: Window watchdog stopped ...
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... Unique ID 8 Unique ID STM8TL53C4/G4 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm ...
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STM8TL53xx 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 9.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical parameters 9.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin input voltage 9.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage ...
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STM8TL53xx Table 12. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any other I/O and control pin I IO Output current source by any I/Os and control pin ...
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Electrical parameters 9.3.2 Power supply Figure 8. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins ...
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STM8TL53xx 9.3.4 Supply current characteristics Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at V ● All peripherals are disabled except if explicitly mentioned Subject to ...
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Electrical parameters Table 17. Total current consumption in Wait mode Symbol Parameter Supply I current in DD(Wait) Wait mode 1. Based on characterization results, unless otherwise specified. 2. Maximum values are given for T Figure 10. I DD(Wait) Table 18. ...
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STM8TL53xx Figure 11. I DD(Halt) 0.0009 0.0008 0.0007 0.0006 0.0005 0.0004 0.0003 0.0002 0.0001 0 1.6 Current consumption of on-chip peripherals Measurement made for f Table 19. Peripheral current consumption Symbol I DD(TIM2) I DD(TIM3) I DD(TIM4) I DD(USART) I ...
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Electrical parameters Table 20. ProxSense peripheral current consumption Symbol I DD(PXS) 1. Data based on characterization, not tested in production 9.3.5 Internal clock source characteristics The parameters given in temperature and V V and High speed ...
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STM8TL53xx Low speed internal RC oscillator (LSI) Table 23. LSI oscillator characteristics Symbol f Frequency LSI LSI oscillator frequency f (2) drift(LSI) drift 1. 3 For each individual part, this value ...
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Electrical parameters Table 27. Data memory endurance & retention Parameter Endurance Data retention 1. Data based on characterization results, not tested in production. 2. Data based on characterization performed on the whole data memory (2 Kbytes). 9.3.7 I/O port pin ...
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STM8TL53xx Output driving current Subject to general operating conditions for V Table 29. Output driving current (high sink ports) I/O type Symbol (1) V Output low level voltage for an I/O pin OL Standard (2) V Output high level voltage ...
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Electrical parameters NRST pin The NRST pin input driver is CMOS. A permanent pull-up is present which is the same as R (see Table 28 on page PU Subject to general operating conditions for V Table 30. NRST pin characteristics ...
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STM8TL53xx 9.3.8 Communication interfaces Serial peripheral interface (SPI) The parameters given in temperature, f MASTER Section 9.3.1 on page more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 31. SPI characteristics Symbol Parameter f SCK SPI ...
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Electrical parameters Figure 13. SPI timing diagram - slave mode and CPHA = 0 Figure 14. SPI timing diagram - slave mode and CPHA = 1 1. Measurement points are done at CMOS levels: 0.3 V 48/62 (1) and 0.7 ...
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STM8TL53xx Figure 15. SPI timing diagram - master mode 1. Measurement points are done at CMOS levels: 0.3 V (1) and 0 DD. Doc ID 022344 Rev 1 Electrical parameters 49/62 ...
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... Electrical parameters Inter IC control interface (I2C) Subject to general operating conditions for V The STM8TL53C4/G4 I2C interface meets the requirements of the Standard I communication protocol described in the following table with the restrictions mentioned below. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL) ...
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STM8TL53xx Figure 16. Typical application with BUS SDA t f(SDA) SCL t h(STA) 1. Measurement points are done at CMOS levels: 0 9.3.9 EMC characteristics Susceptibility tests are performed on a sample 36 basis ...
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Electrical parameters Table 33. EMS data Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to ...
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STM8TL53xx Static latch-up ● LU: 3 complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O ...
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Package characteristics 10 Package characteristics ® 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK an ST trademark. 10.2 Package mechanical data ...
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STM8TL53xx Figure 18. UFQFPN48 recommended footprint 1. Drawing is not to scale 2. Dimensions are in millimeters Doc ID 022344 Rev 1 Package characteristics 55/62 ...
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Package characteristics Table 38. UFQFPN48 - 48-lead ultra thin fine pitch quad flat no-lead package (7x7), package mechanical data Dim. Min. A 0.800 0.180 D 6.850 6.850 E1 ...
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STM8TL53xx Figure 19. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4x4) and UFQFPN28 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 3. All leads/pads should also be soldered to the ...
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Device ordering information 11 Device ordering information Figure 20. STM8TL53xx ordering information scheme Example: Device type STM8 microcontroller family Product type T = Touch Sensing Sub-family type L53 = Projected capacitive sub-family Pin count pins C = ...
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... Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs Kbytes of code is available ...
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STM8 development tools 12.1.2 STM-STUDIO STM-STUDIO helps debug and diagnose STM8 and STM32 applications while they are running by reading and displaying their variables in real-time. STM-STUDIO perfectly complements traditional debugging tools to fine tune applications well suited ...
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STM8TL53xx 13 Revision history Table 40. Document revision history Date 14-Oct-2011 Revision 1 Initial release Doc ID 022344 Rev 1 Revision history Changes 61/62 ...
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