STM8L151K2 STMicroelectronics, STM8L151K2 Datasheet
STM8L151K2
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STM8L151K2 Summary of contents
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MCU Flash 256 B data EEPROM, Features ■ Operating conditions – Operating power supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR) – Temperature range: -40 to ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8L151x2, STM8L151x3 3.15.2 3.15.3 3.16 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8L151x2, STM8L151x3 List of tables Table 1. Low density STM8L15xxx low power device features and peripheral counts Table 2. Timer feature comparison . . . . . . . ...
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List of tables Table 48. ADC1 accuracy with VDDA = VREF ...
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STM8L151x2, STM8L151x3 List of figures Figure 1. Low density STM8L151xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 48. UFQFPN20 recommended footprint (dimensions in mm 106 Figure 49. TSSOP20 - ...
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... Low density STM8L15xxx devices: STM8L151x2 and STM8L151x3 microcontrollers with a Flash memory density Kbytes. For further details on the STMicroelectronics Ultralow power family please refer to Section 2.2: Ultralow power continuum on page For detailed information on device operation and registers, refer to the reference manual (RM0031) ...
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Introduction STM8L Ultralow power microcontrollers can operate either from 1.8 to 3.6 V (down to 1. power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to +125 °C temperature ...
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STM8L151x2, STM8L151x3 2 Description The Low density STM8L15xxx Ultralow power devices feature an enhanced STM8 CPU core providing increased processing power ( MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, ...
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... RTC, window watchdog, independent watchdog, 16 MHz 1.8 to 3.6 V (down to 1. power-down) with BOR 1.65 to 3.6 V without BOR − − +85 ° +125 °C UFQFPN32 UFQFPN28 LQFP48 UFQFPN20 Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 STM8L151K2/ STM8L151C2 4 (1) ( (10) (18) (23/28) TSSOP20 UFQFPN32 UFQFPN28 ...
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... STMicroelectronics microcontrollers UtraLowPower strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 µm ultralow leakage process. Note: 1 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices. ...
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Functional overview 3 Functional overview Figure 1. Low density STM8L151xx device block diagram 1. Legend: ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access I²C: Inter-integrated circuit multimaster interface IWDG: Independent watchdog POR/PDR: Power on reset / power down ...
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STM8L151x2, STM8L151x3 3.1 Low power modes The Low density STM8L15x devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Wait mode: The CPU clock is stopped, ...
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Functional overview Architecture and registers ● Harvard architecture ● 3-stage pipeline ● 32-bit wide program memory bus - single cycle fetching most instructions ● X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and ...
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STM8L151x2, STM8L151x3 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1. 3.6 V operating supply voltage (V supply pins must be connected as follows: ● SS1 DD1 I/Os and for ...
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Functional overview 3.4 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features ● Clock prescaler: ...
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STM8L151x2, STM8L151x3 Figure 2. Low density STM8L15x clock tree diagram 3.5 Low power real-time clock The real-time clock (RTC independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, ...
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Functional overview 3.6 Memories The Low density STM8L15x devices have the following main features: ● Kbyte of RAM ● The non-volatile memory is divided into three arrays: – Kbytes of low-density embedded Flash program ...
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STM8L151x2, STM8L151x3 3.10 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls ...
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Functional overview 3.12.1 16-bit general purpose timers ● 16-bit autoreload (AR) up/down-counter ● 7-bit prescaler adjustable to fixed power of 2 ratios (1…128) ● 2 individually configurable capture/compare channels ● PWM mode ● Interrupt capability on various events (capture, compare, ...
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STM8L151x2, STM8L151x3 3.15 Communication interfaces 3.15.1 SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices. ● Maximum speed: 8 Mbit/s (f ● Full duplex synchronous transfers ● Simplex synchronous transfers on 2 lines ...
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Functional overview 3.17 Development support Development tools Development tools for the STM8 microcontrollers include: ● The STice emulation system offering tracing and code profiling ● The STVD high-level language debugger including C compiler, assembler and integrated development environment ● The ...
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STM8L151x2, STM8L151x3 4 Pin description Figure 3. STM8L151Cx LQFP48 package pinout Figure 4. STM8L151Kx UFQFPN32 package pinout Figure 5. STM8L151Gx UFQFPN28 package pinout NRST/PA1 1 21 PA2 20 2 PA3 19 3 PA4 ...
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Pin description Figure 6. STM8L151Fx UFQFPN20 package pinout Figure 7. STM8L151Fx TSSOP20 package pinout 26/111 Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 ...
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STM8L151x2, STM8L151x3 Table 3. Legend/abbreviation for table 4 Type Level Port and control configuration Reset state Table 4. Low density STM8L15xxx pin description Pin number Pin name ( NRST/PA1 PA2/OSC_IN ...
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Pin description Table 4. Low density STM8L15xxx pin description (continued) Pin number Pin name PB5/SPI_SCK /ADC1_IN13 PB6/SPI1_MOSI ADC1_IN12 PB7/SPI1_MISO ADC1_IN11 ...
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STM8L151x2, STM8L151x3 Table 4. Low density STM8L15xxx pin description (continued) Pin number Pin name PD4 ADC1_IN10 PD5/ ADC1_IN9 PD6 ADC1_IN8/RTC_CALIB PD7 ...
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Pin description 1. At power-up, the PA1/NRST pin is a reset input pin with pull-up used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. ...
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STM8L151x2, STM8L151x3 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 8. Memory map 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM ...
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Memory and register map MSB have a fixed value: 0x6. 3. The TS_Factory_CONV_V90 byte represents the LSB of the V have a fixed value: 0x3. 4. Refer to Table 8 for an overview of hardware register mapping, to registers, and ...
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STM8L151x2, STM8L151x3 Table 7. I/O port hardware register map (continued) Address Block 0x00 500A 0x00 500B 0x00 500C Port C 0x00 500D 0x00 500E 0x00 500F 0x00 5010 0x00 5011 Port D 0x00 5012 0x00 5013 0x00 5014 0x00 5015 ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 5055 to 0x00 506F 0x00 5070 0x00 5071 0x00 5072 to 0x00 5074 0x00 5075 0x00 5076 0x00 5077 0x00 5078 0x00 5079 0x00 507A DMA1 ...
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STM8L151x2, STM8L151x3 Table 8. General hardware register map (continued) Address Block 0x00 5084 0x00 5085 0x00 5086 0x00 5087 0x00 5088 0x00 5089 0x00 508A 0x00 508B 0x00 508C 0x00 508D 0x00 508E 0x00 508F 0x00 5090 DMA1 0x00 5091 ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 509D 0x00 509E SYSCFG 0x00 509F 0x00 50A0 0x00 50A1 0x00 50A2 ITC - EXTI 0x00 50A3 0x00 50A4 0x00 50A5 0x00 50A6 0x00 50A7 WFE ...
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STM8L151x2, STM8L151x3 Table 8. General hardware register map (continued) Address Block 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C6 0x00 50C7 0x00 50C8 CLK 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 5140 0x00 5141 0x00 5142 0x00 5143 0x00 5144 0x00 5145 0x00 5146 0x00 5147 0x00 5148 0x00 5149 0x00 514A 0x00 514B 0x00 514C 0x00 ...
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STM8L151x2, STM8L151x3 Table 8. General hardware register map (continued) Address Block 0x00 5160 to 0x00 5163 0x00 5164 0x00 5165 0x00 5166 0x00 5167 to RTC 0x00 5169 0x00 516A 0x00 516B 0x00 516C to 0x00 518F 0x00 5190 0x00 ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x00 5215 0x00 5216 0x00 5217 I2C1 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C ...
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STM8L151x2, STM8L151x3 Table 8. General hardware register map (continued) Address Block 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B TIM2 0x00 525C 0x00 525D ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 5280 0x00 5281 0x00 5282 0x00 5283 0x00 5284 0x00 5285 0x00 5286 0x00 5287 0x00 5288 0x00 5289 0x00 528A 0x00 528B TIM3 0x00 528C ...
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STM8L151x2, STM8L151x3 Table 8. General hardware register map (continued) Address Block 0x00 52E0 0x00 52E1 0x00 52E2 0x00 52E3 0x00 52E4 TIM4 0x00 52E5 0x00 52E6 0x00 52E7 0x00 52E8 0x00 52E9 0x00 52EA to 0x00 52FE 0x00 52FF IRTIM ...
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Memory and register map Table 8. General hardware register map (continued) Address Block 0x00 53C8 to 0x00 542F 0x00 5430 0x00 5431 0x00 5432 0x00 5433 0x00 5434 0x00 5435 0x00 5436 0x00 5437 RI 0x00 5438 0x00 5439 0x00 ...
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STM8L151x2, STM8L151x3 Table 9. CPU/SWIM/debug module/interrupt controller registers Address Block Register Label 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 (1) 0x00 7F05 CPU 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 ...
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Memory and register map Table 9. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register Label 0x00 7F90 DM_BK1RE 0x00 7F91 DM_BK1RH 0x00 7F92 DM_BK1RL 0x00 7F93 DM_BK2RE 0x00 7F94 DM_BK2RH 0x00 7F95 DM DM_BK2RL 0x00 7F96 0x00 7F97 0x00 7F98 ...
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STM8L151x2, STM8L151x3 6 Interrupt vector mapping Table 10. Interrupt mapping IRQ Source Description No. block RESET Reset TRAP Software interrupt (2) 0 TLI External top level interrupt FLASH end of programing/ 1 FLASH write attempted to protected page interrupt DMA1 ...
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Interrupt vector mapping Table 10. Interrupt mapping (continued) IRQ Source Description No. block TIM2 update/overflow/ 19 TIM2 trigger/break interrupt TIM2 capture/ 20 TIM2 compare interrupt TIM3 update/overflow/ 21 TIM3 trigger/break interrupt TIM3 capture/ 22 TIM3 compare interrupt ...
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STM8L151x2, STM8L151x3 7 Electrical parameters 7.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 7.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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Electrical parameters 7.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Pin input voltage 7.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage ...
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STM8L151x2, STM8L151x3 Table 12. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by IR_TIM pin (with high sink LED driver capability Output current sunk by any other ...
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Electrical parameters 7.3 Operating conditions Subject to general operating conditions for V 7.3.1 General operating conditions Table 14. General operating conditions Symbol Parameter System clock (1) f SYSCLK frequency Standard operating V DD voltage Analog operating V DDA voltage Power ...
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STM8L151x2, STM8L151x3 7.3.2 Embedded reset and power control block characteristics Table 15. Embedded reset and power control block characteristics Symbol Parameter V rise time rate DD t VDD V fall time rate DD t Reset release delay TEMP V Power-down ...
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Electrical parameters Figure 11. POR/BOR thresholds Internal NRST 7.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at V ● All peripherals are ...
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STM8L151x2, STM8L151x3 Table 16. Total current consumption in Run mode Para Symbol meter All peripherals OFF, Supply code current I executed DD(RUN) in run from RAM, (3) mode V from DD 1. 3.6 V All peripherals OFF, code ...
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Electrical parameters 4. The run from RAM consumption can be approximated with the linear formula: I (run_from_RAM) = Freq * 90 µA/MHz + 380 µ Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the ...
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STM8L151x2, STM8L151x3 In the following table, data are based on characterization results, unless otherwise specified. Table 17. Total current consumption in Wait mode Symbol Parameter CPU not clocked, all peripherals OFF, Supply code executed I current in from RAM DD(Wait) ...
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Electrical parameters 2. For temperature range 3. 3. Flash is configured in I mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register. DDQ 4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for ...
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STM8L151x2, STM8L151x3 In the following table, data are based on characterization results, unless otherwise specified. Table 18. Total current consumption and timing in Low power run mode at V 3.6 V Symbol Parameter Supply current in Low I DD(LPR) power ...
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Electrical parameters Figure 14. Typ. I 60/111 vs. V (LSI clock source) DD(LPR) DD Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 ...
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STM8L151x2, STM8L151x3 In the following table, data are based on characterization results, unless otherwise specified. Table 19. Total current consumption in Low power wait mode at V Symbol Parameter Supply current in I DD(LPW) Low power wait mode 1. No ...
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Electrical parameters In the following table, data are based on characterization results, unless otherwise specified. Table 20. Total current consumption and timing in Active-halt mode at V Symbol Parameter Supply current in I DD(AH) Active-halt mode Supply current during wakeup ...
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STM8L151x2, STM8L151x3 In the following table, data are based on characterization results, unless otherwise specified. Table 22. Total current consumption and timing in Halt mode at V Symbol Supply current in Halt mode I (Ultra low power ULP bit =1 ...
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Electrical parameters Current consumption of on-chip peripherals Table 23. Peripheral current consumption Symbol I TIM2 supply current DD(TIM2) I TIM3 supply current DD(TIM3) I TIM4 timer supply current DD(TIM4) I USART1 supply current DD(USART1) I SPI1 supply current DD(SPI1) I ...
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STM8L151x2, STM8L151x3 Table 24. Current consumption under external reset Symbol Parameter Supply current under I DD(RST) (1) external reset 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under ...
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Electrical parameters HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the ...
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STM8L151x2, STM8L151x3 LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the ...
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Electrical parameters Internal clock sources Subject to general operating conditions for V High speed internal RC oscillator (HSI) In the following table, data are based on characterization results, not tested in production, unless otherwise specified. Table 29. HSI oscillator characteristics ...
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STM8L151x2, STM8L151x3 Figure 18. Typical HSI frequency vs V Low speed internal RC oscillator (LSI) In the following table, data are based on characterization results, not tested in production. Table 30. LSI oscillator characteristics Symbol f Frequency LSI t LSI ...
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Electrical parameters Figure 19. Typical LSI frequency vs. V 70/111 DD Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 ...
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STM8L151x2, STM8L151x3 7.3.5 Memory characteristics T = -40 to 125 °C unless otherwise specified. A Table 31. RAM and hardware registers Symbol V Data retention mode RM 1. Minimum supply voltage without losing data stored in RAM (in Halt mode ...
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Electrical parameters 7.3.6 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard pins) should be avoided during normal product operation. However order to ...
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STM8L151x2, STM8L151x3 Table 34. I/O static characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys (3) hysteresis I Input leakage current lkg Weak pull-up equivalent R PU (2)(6) resistor ...
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Electrical parameters Figure 20. Typical V Figure 21. Typical V 74/111 and (high sink I/Os and (true open drain I/Os Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 ...
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STM8L151x2, STM8L151x3 Figure 22. Typical pull-up resistance R Figure 23. Typical pull-up current with with Doc ID 018780 Rev 3 Electrical parameters = 75/111 ...
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Electrical parameters Output driving current Subject to general operating conditions for V Table 35. Output driving current (high sink ports) I/O Symbol Type (1) Output low level voltage for an I/O pin V OL (2) V Output high level voltage ...
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STM8L151x2, STM8L151x3 Figure 24. Typ ports) Figure 26. Typ drain ports) Figure 28. Typ sink ports) = 3.0 V (high sink Figure 25. ...
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Electrical parameters NRST pin Subject to general operating conditions for V Table 38. NRST pin characteristics Symbol Parameter V NRST input low level voltage IL(NRST) V NRST input high level voltage IH(NRST) V NRST output low level voltage OL(NRST) V ...
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STM8L151x2, STM8L151x3 Figure 31. Typical NRST pull-up current I The reset network shown in must ensure that the level on the NRST pin can go below the V in Table 38. Otherwise the reset is not taken into account internally. ...
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Electrical parameters 7.3.8 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions summarized in the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39. SPI1 characteristics Symbol Parameter ...
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STM8L151x2, STM8L151x3 Figure 33. SPI1 timing diagram - slave mode and CPHA=0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure 34. SPI1 ...
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Electrical parameters Figure 35. SPI1 timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 82/111 ...
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STM8L151x2, STM8L151x3 Inter IC control interface Subject to general operating conditions for V 2 The STM8L I C interface (I2C1) meets the requirements of the Standard I protocol described in the following table with the restriction ...
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Electrical parameters Figure 36. Typical application with BUS SDA t f(SDA) SCL t h(STA) 1. Measurement points are done at CMOS levels: 0 84/111 2 C bus and timing diagram ...
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STM8L151x2, STM8L151x3 7.3.9 Embedded reference voltage In the following table, data are based on characterization results, not tested in production, unless otherwise specified. Table 41. Reference voltage characteristics Symbol Parameter Internal reference voltage I REFINT consumption ADC1 sampling time when ...
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Electrical parameters 7.3.10 Temperature sensor In the following table, data are based on characterization results, not tested in production, unless otherwise specified. Table 42. TS characteristics Symbol (1) V Sensor reference voltage at 90°C ±5 ° ...
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STM8L151x2, STM8L151x3 In the following table, data are guaranteed by design, not tested in production. Table 44. Comparator 2 characteristics Symbol V Analog supply voltage DDA T Temperature range A V Comparator 2 input voltage range IN t Comparator startup ...
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Electrical parameters 7.3.12 12-bit ADC1 characteristics In the following table, data are guaranteed by design, not tested in production. Table 45. ADC1 characteristics Symbol Parameter V Analog supply voltage DDA Reference supply V REF+ voltage V Lower reference voltage REF- ...
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STM8L151x2, STM8L151x3 Table 45. ADC1 characteristics (continued) Symbol Parameter t Sampling time S t 12-bit conversion time conv Wakeup time from OFF t WKUP state Time before a new (6) t IDLE conversion Internal reference t VREFINT voltage startup time ...
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Electrical parameters In the following three tables, data are guaranteed by characterization result, not tested in production. Table 46. ADC1 accuracy with V Symbol DNL Differential non linearity INL Integral non linearity TUE Total unadjusted error Offset Offset error Gain ...
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STM8L151x2, STM8L151x3 Figure 37. ADC1 accuracy characteristics [1LSB = IDEAL 4095 4094 4093 SSA Figure 38. Typical connection diagram using the ADC1 1. Refer to Table 45 ...
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Electrical parameters Figure 39. Power supply and reference decoupling (V Figure 40. Power supply and reference decoupling (V 92/111 REF+ REF+ Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 V not connected to ) DDA V ) connected to DDA ...
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STM8L151x2, STM8L151x3 Figure 41. Max. dynamic current consumption on V conversion Table 49. R max for f AIN ADC (cycles) (µs) 2.4 V < V DDA 4 0.25 Not allowed 9 0.5625 0 2.0 ...
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Electrical parameters Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the ...
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STM8L151x2, STM8L151x3 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins ...
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Electrical parameters 7.4 Thermal characteristics The maximum chip junction temperature (T Table 14: General operating conditions on page The maximum chip-junction temperature, T the following equation: Where: is the maximum ambient temperature in ° C ● T Amax Θ is ...
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STM8L151x2, STM8L151x3 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with ...
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Option bytes Table 56. Option byte description Option byte No. ROP[7:0] Memory readout protection (ROP) OPT0 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031). UBC[7:0] Size ...
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STM8L151x2, STM8L151x3 Table 56. Option byte description (continued) Option byte No. BOR_ON: 0: Brownout reset off 1: Brownout reset on OPT5 BOR_TH[3:1]: Brownout reset thresholds. Refer to the value of BOR_TH bits. OPTBL[15:0]: This option is checked by the boot ...
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Unique ID 9 Unique ID STM8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the ...
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STM8L151x2, STM8L151x3 10 Package characteristics 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: ...
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Package characteristics 10.2 Package mechanical data Figure 42. LQFP48 – 48-pin low profile quad flat package outline (7x7) Table 58. LQFP48 – 48-pin low profile quad flat package (7x7), package mechanical data Dim. Min A A1 0.05 A2 1.35 b ...
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STM8L151x2, STM8L151x3 Figure 43. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (1)(2)( Seating plane Pin # 0.30 D2 ...
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Package characteristics Figure 45. UFQFPN28 – 28-lead ultra thin fine pitch quad flat no-lead package outline ( Drawing is not to scale. 104/111 Doc ID 018780 Rev 3 STM8L151x2, STM8L151x3 ...
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STM8L151x2, STM8L151x3 Figure 46. UFQFPN28 recommended footprint (dimensions in mm) 1. Drawing is not to scale. Table 60. UFQFPN28 – 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data Dim. Min A 0.500 A1 ...
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Package characteristics Figure 47. UFQFPN20 - 20-lead ultra thin fine pitch quad flat package outline (3x3 Figure 48. UFQFPN20 recommended footprint (dimensions in mm) 1. Drawing is not to scale. 106/111 ...
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STM8L151x2, STM8L151x3 Table 61. UFQFPN20 - 20-lead ultra thin fine pitch quad flat package (3x3) package mechanical data Dim. Min 0.500 A1 0.000 A3 θ 0 ° 0.500 L2 0.300 L3 L4 0.180 b Tolerance ...
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Package characteristics Figure 49. TSSOP20 - 20-pin thin shrink small outline package Table 62. TSSOP20 - 20-pin thin shrink small outline package mechanical data Dim Values in inches ...
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STM8L151x2, STM8L151x3 11 Device ordering information Figure 50. Low density STM8L15xxx ordering information scheme Example: Product class STM8 microcontroller Family type L = Low power Sub-family type 151 = Ultralow power Pin count pins ...
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Revision history 12 Revision history Table 63. Document revision history Date 08-Jun-2011 02-Sep-2011 09-Feb-2012 110/111 Revision 1 Initial release Modified Figure 8: Memory map on page Modified OPT1 description in page 52 Modified t in Table 36: Flash program and ...
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... STM8L151x2, STM8L151x3 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...