STM8S007C8 STMicroelectronics, STM8S007C8 Datasheet
STM8S007C8
Specifications of STM8S007C8
Available stocks
Related parts for STM8S007C8
STM8S007C8 Summary of contents
Page 1
... C interface up to 400 Kbit/s ■ 10-bit ADC with channels ■ I/Os – 38 I/Os including 16 high sink outputs – Highly robust I/O design, immune against current injection – Development support – Single wire interface module (SWIM) and debug module (DM) Doc ID 022171 Rev 2 STM8S007C8 LQFP48 7x7 1/90 www.st.com 1 ...
Page 2
... TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 16 4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.13 Analog-to-digital converter (ADC2 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.14.1 4.14.2 4.14.3 4.14.4 5 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/90 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Doc ID 022171 Rev 2 STM8S007C8 ...
Page 3
... STM8S007C8 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.2.1 10.2.2 11 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.2.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical curves ...
Page 4
... Contents 11.2.2 11.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4/90 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 5
... STM8S007C8 List of tables Table 1. STM8S007xx value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14 Table 3. TIM timer features Table 4. Legend/abbreviations for LQFP48 pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. LQFP48 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8 ...
Page 6
... List of tables Table 49. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 50. Thermal characteristics Table 51. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 7
... STM8S007C8 List of figures Figure 1. STM8S007xx value line block diagram Figure 2. Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. LQFP 48-pin pinout Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 5. Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 8. f versus V CPUmax Figure 9. External capacitor C Figure 10. ...
Page 8
... For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). ● For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). 8/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 9
... STM8S007xx value line features Pin count Max. number of GPIOs (I/O) External interrupt pins Timer CAPCOM channels Timer complementary outputs A/D converter channels HIgh sink I/Os High density Flash program memory Data EEPROM RAM Features Doc ID 022171 Rev 2 Description STM8S007C8 Kbytes 128 bytes 6 Kbytes 9/90 ...
Page 10
... Clock to peripherals and core STM8 core Debug/SWIM SPI UART1 UART3 ADC2 Beeper Doc ID 022171 Rev 2 STM8S007C8 XTAL 1-24 MHz RC int. 16 MHz RC int. 128 kHz Window WDG Independent WDG 64 Kbytes high density program Flash 128 bytes data EEPROM 6 Kbytes RAM Boot ROM ...
Page 11
... STM8S007C8 4 Product overview The following section intends to give an overview of the basic features of the STM8S007xx value line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. ...
Page 12
... MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to 12/90 Figure 2. Doc ID 022171 Rev 2 STM8S007C8 ...
Page 13
... STM8S007C8 The size of the UBC is programmable through the UBC option byte of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: ● Main program memory: 64 Kbytes minus UBC ● User-specific boot code (UBC): Configurable Kbytes The UBC area remains write-protected during in-application programming ...
Page 14
... Peripheral Bit Bit clock PCKEN13 UART3 PCKEN27 PCKEN12 UART1 PCKEN26 PCKEN11 SPI PCKEN25 2 PCKEN10 I C PCKEN24 Doc ID 022171 Rev 2 STM8S007C8 coming from different oscillators Peripheral Peripheral Bit clock clock Reserved PCKEN23 ADC Reserved PCKEN22 AWU Reserved PCKEN21 Reserved Reserved PCKEN20 Reserved ...
Page 15
... STM8S007C8 4.6 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. ● Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. ● ...
Page 16
... TIM2, TIM3 - 16-bit general purpose timers ● 16-bit autoreload (AR) up-counter ● 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 ● Timers with individually configurable capture/compare channels ● PWM mode ● Interrupt sources input capture/output compare overflow/update 16/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 17
... STM8S007C8 4.12 TIM4 - 8-bit basic timer ● 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ● Clock source: CPU clock ● Interrupt source overflow/update Table 3. TIM timer features Counter Timer size (bits) TIM1 16 Any integer from 1 to 65536 ...
Page 18
... LIN master mode ● Emission: Generates 13-bit synch break frame ● Reception: Detects 11-bit break frame 4.14.2 UART3 Main features ● 1 Mbit/s full duplex SCI ● LIN master capable ● High precision baud rate generator 18/90 /16) CPU Doc ID 022171 Rev 2 STM8S007C8 /16) and capable of CPU ...
Page 19
... STM8S007C8 Asynchronous communication (UART mode) ● Full duplex communication - NRZ standard format (mark/space) ● Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless of the input frequency ● Separate enable bits for transmitter and receiver ● Two receiver wakeup modes: – ...
Page 20
... C slave features: – Programmable I – Stop bit detection ● Generation and detection of 7-bit/10-bit addressing and general call ● Supports different communication speeds: – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz) 20/ address detection Doc ID 022171 Rev 2 STM8S007C8 ...
Page 21
... STM8S007C8 5 Pinouts and pin description Figure 3. LQFP 48-pin pinout [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/(HS) PA4 UART1_TX/(HS) PA5 UART1_CK/(HS) PA6 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function) ...
Page 22
... ( Doc ID 022171 Rev 2 STM8S007C8 Alternate Default function alternate after remap function [option bit] Reset Resonator/ X Port A1 crystal in Resonator/ X Port A2 crystal out I/O ground Digital ground 1.8 V regulator capacitor Digital power supply ...
Page 23
... STM8S007C8 Table 5. LQFP48 pin description (continued) Pin name 14 V SSA 15 PB7/AIN7 16 PB6/AIN6 17 PB5/AIN5 18 PB4/AIN4 19 PB3/AIN3 20 PB2/AIN2 21 PB1/AIN1 22 PB0/AIN0 23 PE7/AIN8 24 PE6/AIN9 25 PE5/SPI_NSS 26 PC1/TIM1_CH1 27 PC2/TIM1_CH2 28 PC3/TIM1_CH3 29 PC4/TIM1_CH4 30 PC5/SPI_SCK 31 V SSIO_2 32 V DDIO_2 Input Output S I Port B7 I Port B6 I ...
Page 24
... (1) I Doc ID 022171 Rev 2 STM8S007C8 Default alternate function SPI master X Port C6 out/ slave in SPI master in/ X Port C7 slave out X Port G0 X Port G1 Timer Port E3 break input (2) 2 Port E2 I ...
Page 25
... STM8S007C8 5.1 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers ...
Page 26
... Memory and register map 6 Memory and register map 6.1 Memory map Figure 4. Memory map 26/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 27
... STM8S007C8 Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 6. Flash, Data EEPROM and RAM boundary addresses Memory area Flash program memory RAM Data EEPROM 6.2 Register map Table 7. I/O port hardware register map ...
Page 28
... Port H control register 2 PI_ODR Port I data output latch register PI_IDR Port I input pin value register PI_DDR Port I data direction register PI_CR1 Port I control register 1 PI_CR2 Port I control register 2 Doc ID 022171 Rev 2 STM8S007C8 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
Page 29
... STM8S007C8 Table 8. General hardware register map Address Block 0x00 5050 to 0x00 5059 0x00 505A 0x00 505B 0x00 505C Flash 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to 0x00 5061 0x00 5062 Flash 0x00 5063 0x00 5064 Flash 0x00 5065 to 0x00 509F ...
Page 30
... I 2 I2C_FREQR I C frequency register 2 I2C_OARL I C own address register low 2 I2C_OARH I C own address register high Reserved Doc ID 022171 Rev 2 STM8S007C8 Register name SPI data register C control register 1 C control register 2 Reset status 0x00 0bXXXX XXX0 0x7F 0x7F (2) 0xXX 0x00 ...
Page 31
... STM8S007C8 Table 8. General hardware register map (continued) Address Block 0x00 5216 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D 0x00 521E to 0x00 522F 0x00 5230 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 ...
Page 32
... TIM1 capture/compare register 4 high TIM1_CCR4L TIM1 capture/compare register 4 low TIM1_BKR TIM1 break register TIM1_DTR TIM1 dead-time register TIM1_OISR TIM1 output idle state register Reserved area (147 bytes) Doc ID 022171 Rev 2 STM8S007C8 Register name Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
Page 33
... STM8S007C8 Table 8. General hardware register map (continued) Address Block 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A TIM2 0x00 530B 00 530C0x 0x00 530D 0x00 530E 0x00 530F ...
Page 34
... ADC data register high ADC_DRL ADC data register low ADC_TDRH ADC Schmitt trigger disable register high ADC_TDRL ADC Schmitt trigger disable register low Reserved area (1016 bytes) Doc ID 022171 Rev 2 STM8S007C8 Register name TIM4 counter Reset status 0xFF 0xFF 0x00 0x00 ...
Page 35
... STM8S007C8 Table 9. CPU/SWIM/debug module/interrupt controller registers Address Block Register Label 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 (1) 0x00 7F05 CPU 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F 0x00 7F60 CPU 0x00 7F70 ...
Page 36
... DM debug module control register 1 DM_CR2 DM debug module control register 2 DM_CSR1 DM debug module control/status register 1 DM_CSR2 DM debug module control/status register 2 DM enable function register Reserved area (5 bytes) map. Doc ID 022171 Rev 2 STM8S007C8 Register Name Reset Status 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 ...
Page 37
... STM8S007C8 7 Interrupt vector mapping Table 10. Interrupt mapping IRQ Source Description no. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 AWU Auto wake up from halt 2 CLK Clock controller 3 EXTI0 Port A external interrupts 4 EXTI1 Port B external interrupts 5 EXTI2 Port C external interrupts ...
Page 38
... NUBC[7:0] AFR7 AFR6 AFR5 Reserved NAFR6 NAFR5 NAFR4 Reserved Reserved Reserved Reserved HSECNT[7:0] NHSECNT[7:0] Reserved Reserved Reserved Reserved BL[7:0] NBL[7:0] Doc ID 022171 Rev 2 STM8S007C8 AFR3 AFR2 AFR1 AFR0 NAFR3 NAFR2 NAFR1 NAFR0 LSI IWDG WWDG WWDG _EN _HW _HW _HALT ...
Page 39
... STM8S007C8 Table 12. Option byte description Option byte no. OPT0 OPT1 OPT2 Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area ...
Page 40
... HSE cycles 0xE1: 0.5 HSE cycles Reserved WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 1 wait state is required if f > 16 MHz. CPU 0: No wait state 1: 1 wait state Doc ID 022171 Rev 2 STM8S007C8 ...
Page 41
... STM8S007C8 Table 12. Option byte description (continued) Option byte no. OPTBL Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector ...
Page 42
... Figure 5. Supply current measurement conditions 42/ Figure 3 DDA V DDIO SSA V SSIO Doc ID 022171 Rev 2 STM8S007C8 . °C and (given by A Amax = 25 ° They are given and V are connected DDIO DDA ...
Page 43
... STM8S007C8 9.1.5 Pin loading conditions 9.1.6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Pin loading conditions 9.1.7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin input voltage STM8 pin 50 pF STM8 pin ...
Page 44
... V there is no positive injection current, and the corresponding V 44/90 Ratings V DDA and DDIO ( and ground ( DDIO DDA SS SSIO >V while a negative injection is induced Doc ID 022171 Rev 2 STM8S007C8 Min Max (1) ) -0.3 6.5 ( 0 see Absolute maximum ...
Page 45
... STM8S007C8 Table 14. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin Total output current sourced (sum of all I/O and control pins) for devices with two V ...
Page 46
... Maximum power dissipation parameters is given by the design of the internal regulator. CAP (T ), use the formula Dmax Jmax 84) with the value for T given in Jmax characteristics. Doc ID 022171 Rev 2 STM8S007C8 Conditions Min Max 2.95 5.5 470 3300 0.3 (2) 15 443 ...
Page 47
... STM8S007C8 Figure 8. f CPUmax Table 17. Operating conditions at power-up/power-down Symbol VDD V DD Reset release t TEMP delay Power-on reset V IT+ threshold Brown-out reset V IT- threshold Brown-out reset V HYS(BOR) hysteresis 1. Guaranteed by design, not tested in production. 9.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor C V pin ...
Page 48
... HSI RC osc. (16 MHz/8) MASTER /128 = 125 kHz HSI RC osc. (16 MHz) MASTER /128 = MASTER HSI RC osc. (16 MHz/8) = 128 kHz LSI RC osc. (128 kHz) MASTER Doc ID 022171 Rev 2 STM8S007C8 Figure 5 on page 42 (no load the WAITSTATE option bit is set. and and ...
Page 49
... STM8S007C8 Table 19. Total current consumption with code execution in run mode at V Symbol Parameter CPU Supply CPU current in run mode, code executed CPU from RAM CPU 15.625 kHz CPU I DD(RUN CPU Supply CPU current in run mode, ...
Page 50
... HSE user ext. clock (24 MHz) HSE crystal osc. (16 MHz MHz HSE user ext. clock (16 MHz) MASTER HSI RC osc. (16 MHz) /128 = 125 kHz HSI RC osc. (16 MHz) MASTER /128 = MASTER HSI RC osc. (16 MHz/8) /128 = MASTER LSI RC osc. (128 kHz) Doc ID 022171 Rev 2 STM8S007C8 = Typ 2.4 1.8 2.0 1.4 1.2 1.0 (2) 0.55 0 Typ 2 ...
Page 51
... STM8S007C8 Total current consumption in active halt mode Table 22. Total current consumption in active halt mode at V Main voltage Symbol Parameter regulator (MVR) Supply current in I DD(AH) active halt mode 1. Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. ...
Page 52
... MVR voltage (4) regulator on Flash in powerdown (5) mode Flash in operating (5) mode MVR voltage (4) regulator off Flash in powerdown (5) mode (5) Flash in operating mode (5) Flash in powerdown mode Doc ID 022171 Rev 2 STM8S007C8 = -40 to 85° Typ Max 63.5 6 3.3 V Typ 61.5 4.5 Typ Max See note 0.56 (6) (6) 1 ...
Page 53
... STM8S007C8 Total current consumption and timing in forced reset state Table 27. Total current consumption and timing in forced reset state Symbol Parameter I Supply current in reset state DD(R) Reset release to bootloader vector t RESETBL fetch 1. Data guaranteed by design, not tested in production. Current consumption of on-chip peripherals Subject to general operating conditions for V HSI internal RC/f Table 28 ...
Page 54
... Electrical characteristics Current consumption curves Figure 10 and Figure 11 RAM. Figure 10. Typ. I Figure 11. Typ. I 54/90 show typical current consumption measured with code executing HSI RC osc, f DD(RUN HSI RC osc, f DD(WFI) DD Doc ID 022171 Rev 2 STM8S007C8 = 16 MHz CPU = 16 MHz CPU ...
Page 55
... STM8S007C8 9.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 29. HSE user external clock characteristics Symbol User external clock source f HSE_ext frequency OSCIN input pin high level (1) V HSEH voltage OSCIN input pin low level ...
Page 56
... Conditions ( pF MHz OSC pF MHz OSC V is stabilized OSCIN Resonator OSCOUT Doc ID 022171 Rev 2 STM8S007C8 Min Typ Max 1 24 220 20 6 (startup) (3) 2 (stabilized) 6 (startup) (3) 1.5 (stabilized value core HSE Consumption ...
Page 57
... STM8S007C8 9.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for V High speed internal RC oscillator (HSI) Table 31. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of HSI oscillator ACC HSI Accuracy of HSI oscillator (factory calibrated) HSI oscillator wakeup t su(HSI) time including calibration ...
Page 58
... LSI oscillator power consumption DD(LSI) 1. Guaranteeed by design, not tested in production. Figure 15. Typical LSI frequency variation vs V 58/90 and T DD Parameter Conditions -1% -2% -3% 2.5 3 3.5 4 4.5 V [V] DD Doc ID 022171 Rev 2 STM8S007C8 . A Min Typ Max 128 ( °C 5 5.5 6 ai15070 Unit kHz µs µA ...
Page 59
... STM8S007C8 9.3.5 Memory characteristics RAM and hardware registers Table 33. RAM and hardware registers Symbol Minimum supply voltage without losing data stored in RAM (in halt mode or under reset hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Table 17 on page 47 ...
Page 60
... Load = 50 pF Standard and high sink I/Os Load = 50 pF ≤ ≤ ≤ ≤ Injection current ±4 mA Doc ID 022171 Rev 2 STM8S007C8 and T unless otherwise specified. All A Min Typ Max -0 700 (2) 20 (2) 125 ± ...
Page 61
... STM8S007C8 Figure 16. Typical V Figure 17. Typical pull-up resistance vs V and temperatures temperatures DD Doc ID 022171 Rev 2 Electrical characteristics 61/90 ...
Page 62
... Conditions Doc ID 022171 Rev 2 STM8S007C8 Min Max Unit 2 V (1) 1 2.8 V (1) 2.1 Max Unit 1 (1) 1.5 V (1) 2 ...
Page 63
... STM8S007C8 Table 38. Output driving current (high sink ports) Symbol Parameter Output low level with 8 pins sunk V Output low level with 4 pins sunk OL Output low level with 4 pins sunk Output high level with 8 pins sourced V Output high level with 4 pins sourced OH Output high level with 4 pins sourced 1 ...
Page 64
... Electrical characteristics Figure 20. Typ. V Figure 21. Typ. V 64/ 3.3 V (standard ports (true open drain ports Doc ID 022171 Rev 2 STM8S007C8 ...
Page 65
... STM8S007C8 Figure 22. Typ. V Figure 23. Typ 3.3 V (true open drain ports (high sink ports Doc ID 022171 Rev 2 Electrical characteristics 65/90 ...
Page 66
... Electrical characteristics Figure 24. Typ. V Figure 25. Typ. V 66/ 3.3 V (high sink ports (standard ports Doc ID 022171 Rev 2 STM8S007C8 ...
Page 67
... STM8S007C8 Figure 26. Typ. V Figure 27. Typ 3.3 V (standard ports (high sink ports Doc ID 022171 Rev 2 Electrical characteristics 67/90 ...
Page 68
... Data guaranteed by design, not tested in production. 68/ 3.3 V (high sink ports and T unless otherwise specified Conditions (1) (1) ( (2) (3) (3) (1) Doc ID 022171 Rev 2 STM8S007C8 1) Min Typ Max -0 500 15 Unit V kΩ µs ...
Page 69
... STM8S007C8 Figure 29. Typical NRST V Figure 30. Typical NRST pull-up resistance vs V and temperatures temperatures DD Doc ID 022171 Rev 2 Electrical characteristics 69/90 ...
Page 70
... The minimum recommended capacity is 10 nF. Figure 32. Recommended reset pin protection External reset circuit (optional) 70/ temperatures DD Figure 32 protects the device against parasitic resets. The user NRST 0.1µF Doc ID 022171 Rev 2 STM8S007C8 max. level specified in IL STM8 Internal reset Filter ...
Page 71
... STM8S007C8 SPI serial peripheral interface 9.3.8 Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions. t MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. SPI characteristics Symbol Parameter f SCK SPI clock frequency ...
Page 72
... OUT h(SI) t c(SCK) t v(SO OUT t h(SI and 0 DD. Doc ID 022171 Rev 2 STM8S007C8 t h(NSS) t r(SCK) t dis(SO) t f(SCK) LSB OUT LSB IN (1) t h(NSS) t r(SCK) t h(SO) t dis(SO) t f(SCK) LSB OUT LSB IN ai14134 ai14135 ...
Page 73
... STM8S007C8 Figure 35. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3 V (1) t c(SCK) t w(SCKH) t w(SCKL) MS BIN h(MI OUT OUT t v(MO) t h(MO) and 0 ...
Page 74
... The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 74/90 Standard mode I Parameter Min 4.7 4.0 250 (3) 0 4.0 4.7 4.0 4 speed (400kHz protocol requirement, not tested in production Doc ID 022171 Rev 2 STM8S007C8 2 2 (1) C Fast mode I C (2) (2) (2) (2) Max Min Max 1.3 0.6 100 (4) (3) 0 900 ...
Page 75
... STM8S007C8 Figure 36. Typical application with I 1. Measurement points are made at CMOS levels: 0 bus and timing diagram and 0 Doc ID 022171 Rev 2 Electrical characteristics 75/90 ...
Page 76
... ADC MHz ADC MHz ADC MHz ADC (3 pF max) can be charged/discharged by the external AIN , changes of the analog input voltage have no effect on S depend on programming. S Doc ID 022171 Rev 2 STM8S007C8 , and T unless otherwise MASTER A Min Typ Max 5.5 (1) 2.75 V ...
Page 77
... STM8S007C8 Table 43. ADC accuracy with R Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L 1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input ...
Page 78
... SSA 1LSB = ---------------------------------------- - IDEAL 1024 1021 LSB IDEAL SSA 0.6V R AIN AINx C V AIN T 0.6V Doc ID 022171 Rev 2 STM8S007C8 E G (2) (3) ( 1021102210231024 V DDA STM8 10-bit A/D conversion I L ±1µA C ADC ...
Page 79
... STM8S007C8 9.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs ...
Page 80
... MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI level Ratings Conditions = 25°C, conforming JESD22-A114 = 25°C, conforming JESD22-C101 Doc ID 022171 Rev 2 STM8S007C8 (1) Max f /f HSE CPU Unit 16 MHz/ 16 MHz/ 24 MHz/ 8 MHz 16 MHz 24 MHz ...
Page 81
... STM8S007C8 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: ● A supply overvoltage (applied to each power supply pin) ● A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181 ...
Page 82
... Package characteristics 10 Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® trademark. 82/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 83
... STM8S007C8 10.1 Package mechanical data Figure 39. 48-pin low profile quad flat package ( Pin 1 identification 1 Table 49. 48-pin low profile quad flat package mechanical data Symbol ccc 1. Values in inches are converted from mm and rounded to four decimal places. ...
Page 84
... Celsius, may be calculated Jmax x Θ ) Dmax JA and P (P INTmax I/Omax Dmax and V , expressed in Watts. This is the maximum chip Σ(( and taking account of the actual OH) OH (1) Parameter Doc ID 022171 Rev 2 STM8S007C8 = INTmax I/Omax /I OL Value 57 and OL Unit °C/W ...
Page 85
... STM8S007C8 10.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 40: STM8S007xx value line ordering information The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: ● ...
Page 86
... Power supply follower managing application voltages between 1.62 to 5.5 V ● Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ● Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. 86/90 Doc ID 022171 Rev 2 STM8S007C8 ...
Page 87
... STM8S007C8 11.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs Kbytes of code is available ...
Page 88
... For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 2. Refer to Table 1: STM8S007xx value line features 88/90 STM8 (2) for detailed description. Doc ID 022171 Rev 2 STM8S007C8 (1) S 007 ...
Page 89
... STM8S007C8 13 Revision history Table 51. Document revision history Date 31-Oct-2011 06-Jan-2012 Revision 1 Initial release. Table 34: Flash program memory/data EEPROM V condition; updated Table 39: NRST pin characteristics: updated typ and max values of the NRST Pull-up resistor. Doc ID 022171 Rev 2 Revision history Changes memory: updated parameters ...
Page 90
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 90/90 Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 022171 Rev 2 STM8S007C8 ...