ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 62
ST7263BH2
Manufacturer Part Number
ST7263BH2
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST7263BH6.pdf
(186 pages)
Specifications of ST7263BH2
4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection
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On-chip peripherals
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A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 29. Counter timing diagram, internal clock divided by 2
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 30. Counter timing diagram, internal clock divided by 4
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 31. Counter timing diagram, internal clock divided by 8
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
TIMER OVERFLOW FLAG (TOF)
TIMER OVERFLOW FLAG (TOF)
TIMER OVERFLOW FLAG (TOF)
COUNTER REGISTER
COUNTER REGISTER
COUNTER REGISTER
INTERNAL RESET
INTERNAL RESET
INTERNAL RESET
TIMER CLOCK
CPU CLOCK
TIMER CLOCK
TIMER CLOCK
CPU CLOCK
CPU CLOCK
Doc ID 7516 Rev 8
FFFC
FFFC
FFFD FFFE FFFF 0000 0001 0002 0003
FFFD
FFFD
0000
0001
0000
ST7263Bxx
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