ST7263BK2 STMicroelectronics, ST7263BK2 Datasheet - Page 71

• Manufacturer Part Number: ST7263BK2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
Note:
1
2
3
4
5
Figure 40. Pulse width modulation cycle
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OC
the following formula:
Where:
t = Signal or pulse period (in seconds)
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t = Signal or pulse period (in seconds)
f
The output Compare 2 event causes the counter to be initialized to FFFCh (See
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
CPU
EXT
= External timer clock frequency (in hertz)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see
i
R register value required for a specific timing application can be calculated using
Counter
= OC1R
Counter
= OC2R
When
When
Doc ID 7516 Rev 8
OCiR Value =
Pulse Width Modulation cycle
OCiR =
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
t
ICF1 bit is set
*
to FFFCh
f
EXT
PRESC
t
*
f
CPU
-5
- 5
On-chip peripherals
Table
24)
Figure
71/186
39)