ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 155

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
When Px.n is programmed as an Output:
(Figure
– The Output Buffer is turned on in an Open-drain
– The data stored in the Output Master Latch is
When Px.n is programmed as Bidirectional:
(Figure
– The Output Buffer is turned on in an Open-Drain
– The data present on the I/O pin is sampled into
– The data stored in the Output Master Latch is
WARNING: Due to the fact that in bidirectional
mode the external pin is read instead of the output
latch, particular care must be taken with arithme-
tic/logic and Boolean instructions performed on a
bidirectional port pin.
These instructions use a read-modify-write se-
quence, and the result written in the port register
depends on the logical level present on the exter-
nal pin.
This may bring unwanted modifications to the port
output register content.
For example:
Port register content, 0Fh
external port value, 03h
(Bits 3 and 2 are externally forced to 0)
A bset instruction on bit 7 will return:
Port register content, 83h
external port value, 83h
(Bits 3 and 2 have been cleared).
To avoid this situation, it is suggested that all oper-
ations on a port, using at least one bit in bidirec-
tional mode, are performed on a copy of the port
register, then transferring the result with a load in-
struction to the I/O port.
When Px.n is programmed as a digital Alter-
nate Function Output:
(Figure
– The Output Buffer is turned on in an Open-Drain
or Push-pull configuration.
copied both into the Input Latch and into the Out-
put Slave Latch, driving the I/O pin, at the end of
the execution of the instruction.
or Weak Pull-up configuration (except when dis-
abled in hardware).
the Input Latch at the beginning of the execution
of the instruction.
copied into the Output Slave Latch, driving the I/
O pin, at the end of the execution of the instruc-
tion.
or Push-Pull configuration.
83)
84)
85)
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
– The data present on the I/O pin is sampled into
– The signal from an on-chip function is allowed to
Figure 84. Bidirectional Configuration
n
n
Figure 85. Alternate Function Configuration
n
n
n
n
n
n
the Input Latch at the beginning of the execution
of the instruction.
load the Output Slave Latch driving the I/O pin.
Signal timing is under control of the alternate
function. If no alternate function is connected to
Px.n, the I/O pin is driven to a high level when in
Push-Pull configuration, and to a high imped-
ance state when in open drain configuration.
WEAK PULL-UP
OPEN DRAIN
OPEN DRAIN
PUSH-PULL
PERIPHERAL
OUTPUT MASTER LATCH
OUTPUT SLAVE LATCH
OUTPUT
OUTPUT SLAVE LATCH
FROM
INTERNAL DATA BUS
INTERNAL DATA BUS
I/O PIN
I/O PIN
INPUT LATCH
INPUT LATCH
(or Schmitt Trigger)
(or Schmitt Trigger)
TO PERIPHERAL
INTERRUPTS
INPUTS AND
TO PERIPHERAL
INTERRUPTS
INPUTS AND
TTL
TTL
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