ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 211

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

MOTOR CONTROLLER (Cont’d)
Effect on PWM generator: the PWM generator
12-bit counter is reset as soon as CKE = 0; this en-
sures that the PWM signals start properly in all
cases. When these bits are set, all registers with
preload on Update event are transferred to active
registers.
Bit 5 = SR: Sensor ON/OFF.
0: Sensorless mode
1: Position Sensor mode
Table 57. Sensor Mode Selection
See also
Bit 4 = DAC: Direct Access to phase state register.
0: No Direct Access (reset value). In this mode the
1: Direct Access enabled. In this mode, write a val-
Note: In Direct Access Mode (DAC bit is set in
SR
bit
0
1
preload value of the MPHST and MCRB regis-
ters is taken into account at the C event.
ue in the MPHST register to access the outputs
directly.
MCRA register), a C event is generated as soon
as there is a write access to the OO[5:0] bits in
MPHST register. In this case, the PWM low/high
selection is done by the OS0 bit in the MCRB
register.
not used
Sensors
Sensors
Mode
used
Table 61
disabled
OS[2:0]
enabled
OS[2:0]
OS1
bits
bits
and
Table 62
“Between C
“Between C
and “between Z&C
and “between Z&C
“between D&Z” behaviour
Behaviour of the output
haviour
haviour
PWM
n
n
&D” behaviour,
&Z” behaviour
n+1
n+1
” be-
” be-
Table 58. DAC Bit Meaning
Bit 3 = V0C1: Voltage/Current Mode
0: Voltage Mode
1: Current Mode
Bit 2 = SWA: Switched/Autoswitched Mode
0: Switched Mode
1: Autoswitched Mode
Note 1 : after reset, in autoswitched mode (SWA
=1) , the motor control peripheral is waiting for a C
commutation event.
Note 2: After reset, a C event is immediately gen-
erated when CKE and SWA are simultaneaously
set due to a nil value of MCOMP.
Bit 1 = PZ: Protection from parasitic Zero-crossing
event detection
0: Protection disabled
1: Protection enabled
Note: If the PZ bit is set, the Z event filter
(ZEF[3:0] in the MZFR register is ignored.
Bit 0 = DCB: Data Capture bit
0: Use MZPRV (Z
1: Use MZREG (Z
Table 59. Multiplier Result
MOE
DCB bit
bit
0
1
1
0
1
DAC
bit
0
1
x
MCOMP = MWGHT x MZREG / 256
MCOMP = MWGHT x MZPRV / 256
MPHST register value (depending on
Reset state depending on the option
N
N
MPOL, MPAR register values and
-1) for multiplication
) for multiplication
PWM setting) see
Commutation Delay
ST7MC1xx/ST7MC2xx
Effect on Output
running mode.
Standard
bit
Table 74
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