ST7MC1K2 STMicroelectronics, ST7MC1K2 Datasheet - Page 172
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ST7MC1K2
Manufacturer Part Number
ST7MC1K2
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC1K2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
generation. Otherwise, the C event will never oc-
cur.
Note 4: When simulated commutation mode is en-
abled, the built-in check is active, so if the value
written in the MCOMP register is less than or equal
to MTIM, the C event is generated and the data in
the MCOMP register are overwritten by the MTIM
value.
Auto-updated Step Ratio Register:
a) In switched mode: the MTIM timer is driven by
software only and any prescaler change has to be
done by software (see
b) In autoswitched mode: an auto-updated pres-
caler always configures the MTIM timer for best
accuracy.
ing the Step Ratio bits:
– When the MTIM timer value reaches 100h, the
– When a Z-event occurs, if the MTIM timer value
– If the prescaler contents reach the value 0, it can
172/309
1
prescaler is automatically incremented in order
to slow down the MTIM timer and avoid an over-
flow. To keep consistent values, the MTIM regis-
ter and all the relevant registers are shifted right
(divided by two). The RPI bit in the MISR register
is set and an interrupt is generated (if RIM is set).
The timer restarts counting from its median value
0x80h and if the TES[1:0] bits = 00, the OI bit in
the MCRC register is set.
is below 55h, the prescaler is automatically dec-
remented in order to speed up the MTIM timer
and keep precision better than 1.2%. The MTIM
register and all the relevant registers are shifted
left (multiplied by two). The RMI bit in the MISR
register is set and an interrupt is generated if RIM
is set.
no longer be automatically decremented, the
MTC continues working with the same prescaler
value, i.e. with a lower accuracy. No RMI in-
terrrupt can be generated.
Figure 92
shows the process of updat-
page 169
for more details).
– If the prescaler contents reach the value 15, it
The automatically updated registers are: MTIM,
MZREG, MZPRV, MCOMP and MDREG. Access
to these registers is summarized in
10.6.7.3 Debug Option
In both Switched Mode and Autoswitched Mode,
setting the bit DG in MPWME register enables the
Debug Option. This option consists of outputting
the C, D and Z signals in real time on pins MCZEM
and MCDEM. This is very useful during the debug
phase of the application.
nals output on pins MCDEM and MCZEM with the
debug option.
Note 1: When the delay coefficient equals 0/256
(C event immediately after Z event), a glitch ap-
pears on MCZEM pin to be able to see the event
even in this case.
This option is also available in Speed measure-
ment mode with different signal outputs (see
ure
– MCDEM toggles when a capture event is gener-
– MCZEM toggles every time a U event is gener-
These signals are only available if the TES[1:0]
bits = 10, 01 or 11.
Note 2: In sensor mode, the MCDEM output pin
toggles at each C event. The MCZEM pin outputs
the Z event.
can no longer be automatically incremented.
When the timer reaches the value FFh, the pres-
caler and all the relevant registers remain un-
changed and no interrupt is generated, the timer
restarts counting from 0x00h and if the TES[1:0]
bits = 00, the OI bit in the MCRC register is set at
each overflow (it has to be reset by software).
The RPI bit is no longer set. The PWM is still gen-
erated and the D and Z detection circuitry still
work, enabling the capture of the maximum timer
value.
ated,
ated.
94):
Figure 94
shows the sig-
Table
41.
Fig-
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