LNBH26 STMicroelectronics, LNBH26 Datasheet - Page 9

• Manufacturer Part Number: LNBH26
• Description: Dual LNB supply and control IC with step-up and I2C interface
• Manufacturer: STMicroelectronics

LNBH26
2.12
2.13
2.14
2.15
2.16
TMON: 22 kHz tone diagnostic
The 22 kHz tone can be internally detected and monitored if one (or both) DETIN pin are
connected to the LNB output bus (see
The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 kHz
tone amplitude and/or the tone frequency is out of the guaranteed limits (see
corresponding TMON I²C bit is set to “1”.
TDET: 22 kHz tone detection
When a 22 kHz tone presence is detected on one DETIN pin, the corresponding TDET I²C
bit is set to “1”.
IMON: minimum output current diagnostic
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) each LNBH26 section is provided with a minimum output current flag
by the corresponding IMON I²C bit, accessible in read mode, which is set to “1” if the output
current is lower than 12 mA (typ.). It is recommended to use the IMON function only with the
22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the
output current is below the minimum current threshold. To activate the IMON diagnostic
function, set to “1” the EN_IMON I²C bit in the DATA4 register. Be aware that as soon as the
IMON function is activated by means of EN_IMON=1, the V
21 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be
sure that the LNBH26 output has the higher voltage present in the LNB bus. Do not use this
function in an application environment where a 21 V voltage level is not supported by other
peripherals connected to the LNB bus.
PDO: overcurrent detection on output pull-down stage
When an overcurrent occurs on one section pull-down output stage due to an external
voltage source greater than the LNBH26 nominal V
I
due to an external voltage source presence on the LNB output (V
For current threshold and deglitch time details, see
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH26 is automatically reset at power-on. As long as the
V
not respond to any I²C command and all DATA register bits are initialized to zeroes,
therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C
interface becomes operative and the DATA registers can be configured by the main
microprocessor.
SINK_TIME_OUT
CC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
(10 ms typ.), the corresponding PDO I²C bit is set to “1”. This may happen
Doc ID 022771 Rev 1
Application information (valid for each section A/B)
Figure 7
) through a decoupling capacitor.
OUT
Table 13
, and for a time longer than
OUT
.
is immediately increased to
OUT
pin).
Table 19
), the
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