STD40NF3LL STMicroelectronics, STD40NF3LL Datasheet

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STD40NF3LL

Manufacturer Part Number
STD40NF3LL
Description
N-CHANNEL 30V - 0.0095 OHM - 40A DPAK LOW GATE CHARGE STripFET POWER MOSFET
Manufacturer
STMicroelectronics
Datasheet

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STD40NF3LLT4
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Order codes
General features
Description
This application specific Power MOSFET is the
third generation of STMicroelectronics unique
"Single Feature Size™" strip-based process. The
resulting transistor shows the best trade-off
between on-resistance and gate charge. When
used as high and low side in buck regulators, it
gives the best performance in terms of both
conduction and switching losses. This is
extremely important for motherboards where fast
switching and high efficiency are of paramount
importance.
Applications
February 2007
STD40NF3LL
Logic level device
Optimal R
Conduction losses reduced
Switching losses reduced
Low threshold drive
Switching application
Type
STD40NF3LLT4
Part number
DS(on)
x Q
V
30V
DSS
g
trade-off
Low gate charge STripFET™ II Power MOSFET
<0.011Ω
R
DS(on)
D40NF3LL@
Marking
40A
I
N-channel 30V - 0.009Ω - 40A - DPAK
D
Rev 5
Internal schematic diagram
Package
DPAK
STD40NF3LL
DPAK
1
3
Tape & reel
Packaging
www.st.com
1/13
13

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STD40NF3LL Summary of contents

Page 1

... Order codes Part number STD40NF3LLT4 February 2007 N-channel 30V - 0.009Ω - 40A - DPAK Low gate charge STripFET™ II Power MOSFET R I DS(on) D <0.011Ω 40A Internal schematic diagram Marking D40NF3LL@ Rev 5 STD40NF3LL 3 1 DPAK Package Packaging DPAK Tape & reel 1/13 www.st.com 13 ...

Page 2

... Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/ STD40NF3LL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ...

Page 3

... STD40NF3LL 1 Electrical ratings Table 1. Absolute maximum ratings Symbol V Drain-source voltage ( Drain-gate voltage (R DGR V Gate- source voltage GS (1) I Drain current (continuous Drain current (continuous (2) I Drain current (pulsed Total dissipation at T tot Derating Factor (3) dv/dt Peak diode recovery voltage slope ...

Page 4

... V = 25V 1MHz 15V 4.7Ω (see Figure 13) = 15V 4.5V (see Figure 14) STD40NF3LL Min. Typ. Max ±100 = 250µ 20A 0.0090 0.0110 = 10A 0.0115 0.0135 Min. Typ. Max. = 20A 23 1650 540 130 23 = 20A 156 =4 ...

Page 5

... STD40NF3LL Table 5. Source drain diode Symbol Source-drain current I SD Source-drain current (1) I SDM (pulsed) (2) V Forward on voltage SD t Reverse recovery time rr Q Reverse recovery charge rr I Reverse recovery current RRM 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% ...

Page 6

... Electrical characteristics 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 3. Output characteristics Figure 5. Transconductance 6/13 Figure 2. Thermal impedance Figure 4. Transfer characteristics Figure 6. Static drain-source on resistance STD40NF3LL ...

Page 7

... STD40NF3LL Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Electrical characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized breakdown voltage vs. temperature 7/13 ...

Page 8

... Test circuit Figure 13. Switching times test circuit for resistive load Figure 15. Test circuit for inductive load switching and diode recovery times Figure 17. Unclamped inductive waveform 8/13 Figure 14. Gate charge test circuit Figure 16. Unclamped Inductive load test circuit Figure 18. Switching time waveform STD40NF3LL ...

Page 9

... STD40NF3LL 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 10

... TYP MAX. 2.2 2.4 0.9 1.1 0.03 0.23 0.64 0.9 5.2 5.4 0.45 0.6 0.48 0.6 6 6.2 5.1 6.4 6.6 4.7 2.28 4.4 4.6 9.35 10.1 1 2.8 0.8 0.6 1 0.2 0° 8° STD40NF3LL inch MIN. TYP. MAX. 0.086 0.094 0.035 0.043 0.001 0.009 0.025 0.035 0.204 0.212 0.017 0.023 0.019 0.023 0.236 0.244 0.200 0.252 0.260 0.185 0.090 0.173 0.181 0.368 0.397 0.039 0.110 0.031 0.023 0.039 0.008 0° ...

Page 11

... STD40NF3LL 5 Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE MECHANICAL DATA mm DIM. MIN. A0 6 1.5 D1 1.5 E 1.65 F 7.4 K0 2.55 P0 3.9 P1 7 15.7 TAPE AND REEL SHIPMENT inch MAX. MIN. MAX. 7 0.267 0.275 10.6 0.409 0.417 12.1 0.476 1.6 0.059 0.063 0.059 1.85 0.065 0.073 7.6 0.291 0.299 2 ...

Page 12

... Revision history 6 Revision history Table 6. Revision history Date 21-Jun-2004 11-Jul-2006 20-Feb-2007 12/13 Revision New datasheet according to PCN DSG/CT/2C13 3 marking:D40NF3LL@ 4 New template, no content change 5 Typo mistake on page 1 STD40NF3LL Changes ...

Page 13

... STD40NF3LL Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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