DS2431-A1 Maxim, DS2431-A1 Datasheet - Page 3

• Manufacturer Part Number: DS2431-A1
• Description: The DS2431-A1 is an AEC-Q100 Grade 1 qualified version of the DS2431
• Manufacturer: Maxim

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: After V
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
Note 14: Defines maximum possible bit rate. Equal to t
Note 15: Interval after t
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
Note 18: Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming inter-
Note 19: Interval begins t
Note 20: Write-cycle endurance is degraded as T
Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22: Data retention is degraded as T
Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
Specifications at T
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V
up the data line, 2.5µs after V
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
capacitive loading on I/O. Lower V
of V
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less than or equal to V
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Minimum limit is t
maximum duration for the master to pull the line low is t
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
val should be such that the voltage at I/O is greater than or equal to V
low-impedance bypass of R
Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the cur-
rent drawn by the device has returned from I
data sheet limit at operating temperature range is established by reliability testing.
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
TL
, V
TL
TH
, V
TH
, and V
TH
is crossed during a rising edge on I/O, the voltage on I/O must drop by at least V
_______________________________________________________________________________________
, and V
RSTL
HY
REHMAX
PDHMAX
HY
A
are a function of the internal supply voltage, which is a function of V
during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS2431-A1 present.
= -40°C are guaranteed by design only and not production tested.
.
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid Copy
; maximum limit is t
PUP
PUP
, which can be activated during programming, may need to be added.
A
has been applied, the parasite capacitance does not affect normal communications.
increases.
PUP
, higher R
A
increases.
PDHMIN
PROG
for Automotive Applications
W0LMIN
PUP
to I
, shorter t
+ t
1024-Bit, 1-Wire EEPROM
+ t
L
ILMAX
.
PDLMIN
W1LMAX
RECMIN
REH
at all times the master is driving I/O to a logic-0 level.
REC
.
after V
.
+ t
, and heavier capacitive loading all lead to lower values
F
- ε and t
PUP
TH
PUPMIN
has been reached on the preceding rising edge.
is first applied. If a 2.2kΩ resistor is used to pull
W0LMAX
. If V
PUP
+ t
in the system is close to V
PUP
F
- ε, respectively.
HY
, R
to be detected as logic 0.
PUP
RLMAX
, 1-Wire timing, and
IL
IL
+ t
to V
to the input-high
F
.
TH
. The actual
PUPMIN
, a
3