DS28E04-100 Maxim, DS28E04-100 Datasheet - Page 13

• Manufacturer Part Number: DS28E04-100
• Description: The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs
• Manufacturer: Maxim

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
MEMORY/CONTROL FUNCTION COMMANDS
The Memory/Control Function Flow Chart (Figure 9) describes the protocols necessary to access the memory and
the PIO pins of the DS28E04-100. Examples on how to use these functions are included at the end of this
document. The communication between master and DS28E04-100 takes place either at standard speed (default,
OD = 0) or at Overdrive peed (OD = 1). If not explicitly set into the Overdrive Mode, the DS28E04-100 powers up in
standard speed.
WRITE SCRATCHPAD COMMAND [0Fh]
The Write Scratchpad command applies to the data memory, and the writeable addresses in the register page.
After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by
the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T4:T0.
The ending offset (E4:E0) is the byte offset at which the master stops writing data. Only full data bytes are
accepted. If the last data byte is incomplete, its content will be ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command, the CRC generator inside the DS28E04-100 (Figure 18)
calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent
by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then
shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses (TA1 and TA2) as
supplied by the master, and all the data bytes. The master may end the Write Scratchpad command at any time.
However, if the end of the scratchpad is reached (E4:E0 = 11111b), the master can send 16 read-time slots and
receive the CRC generated by the DS28E04-100.
If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in
memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad
is loaded with the bitwise logical AND of the transmitted data and data already in memory.
READ SCRATCHPAD COMMAND [AAh]
The Read Scratchpad command allows verification of the target address and the scratchpad data. After issuing the
command code, the master begins reading. The first two bytes are the target address. The next byte is the ending
offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master
originally sent. This is of particular importance if the target address is within the register page or a page in either
Write-Protected or EPROM modes. See the Write Scratchpad description for details. The master should read
E4:E0-T4:T0+1 bytes, after which it receives the inverted CRC16, based on data as it was sent by the DS28E04-
100. If the master continues reading after the CRC, all data will be logic 1s.
COPY SCRATCHPAD [55h]
The Copy Scratchpad command is used to copy data from the scratchpad to the data memory and the writable
sections of the Register Page. After issuing the Copy Scratchpad command, the master must provide a 3-byte
authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command.
This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that
order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy-
protected, the AA (Authorization Accepted) flag is set and the copy begins. The data to be copied is determined by
the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied
to memory, starting at the target address. Anywhere from 1 to 32 bytes can be copied with this command. The
device’s internal data transfer takes 10ms maximum during which the voltage on the 1-Wire bus must not fall below
2.8V. After waiting 10ms, the master may issue read time slots to receive AAh confirmation bytes until the master
issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA
flag will not be set.
13 of 37