DS28E04-100 Maxim, DS28E04-100 Datasheet - Page 4

• Manufacturer Part Number: DS28E04-100
• Description: The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs
• Manufacturer: Maxim

Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
1)
PIN DESCRIPTION
DETAILED DESCRIPTION
The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven
external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as open-
drain and provide an on-resistance of 100Ω max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the
scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the
scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory
location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this
number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number
guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04-
100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The
DS28E04-100 has an optional V
parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of
the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of
modular systems such as central-office switches, cellular base stations, access products, optical network units, and
PBXs, and accessory/PC board identification.
t
t
t
t
t
Intentional change, longer recovery time requirement due to modified 1-Wire front end.
W0L
SLOT
RSTL
PDH
PDL
PARAMETER
5, 12
6, 11
PIN
(incl. t
10
13
14
15
16
1
2
3
4
7
8
9
ε in Figure 16 represents the time required for the pullup circuitry to pull the voltage on IO up from V
duration for the master to pull the line low is t
δ in Figure 16 represents the time required for the pullup circuitry to pull the voltage on IO up from V
of the bus master. The actual maximum duration for the master to pull the line low is t
Current drawn during the EEPROM programming interval. If the device does not get V
programming interval should be such that the voltage at IO is greater than or equal to V
Vpup(min) then a low-impedance bypass of R
The t
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
Not production tested. Guaranteed by design or characterization.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at elevated temperatures
is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
REC
)
PROG
interval begins t
NAME
GND
N.C.
POL
V
A3
A2
A1
A0
P0
P1
A6
A5
A4
IO
CC
STANDARD SPEED
480µs
61µs
15µs
60µs
60µs
MIN
Address bit input (place value = 8), with weak pullup.
Address bit input (place value = 4), with weak pullup.
Address bit input (place value = 2), with weak pullup.
Least significant address bit input (place value = 1), with weak pullup.
Ground Reference
Not Connected
Optional power supply for the chip; leave unconnected or ground if V
is not available.
Power-up polarity (logical state) for P0 and P1; pin has a weak pulldown.
Remote-controlled I/O pin, open drain with weak pulldown.
Remote-controlled I/O pin, open drain with weak pulldown.
Address bit input (place value = 64), with weak pullup.
Address bit input (place value = 32), with weak pullup.
Address bit input (place value = 16), with weak pullup.
1-Wire Bus Interface. Open drain, requires external pullup resistor.
REHmax
PROG
CC
(undef)
(undef)
supply connection. When an external supply is absent, device power is supplied
to I
LEGACY VALUES
240µs
120µs
MAX
60µs
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
L
or I
CCS
, respectively.
OVERDRIVE SPEED
W1LMAX
PUP
48µs
MIN
7µs
2µs
8µs
6µs
that can be activated during programming may need to be added.
+ t
F
4 of 37
- ε and t
(undef)
MAX
80µs
24µs
16µs
6µs
W0LMAX
FUNCTION
+ t
F
- ε respectively.
STANDARD SPEED
65µs
504µs
15µs
60µs
60µs
MIN
1)
RLMAX
CC
PUP
DS28E04-100 VALUES
power, the pullup circuit on IO during the
(undef)
640µs
240µs
120µs
(min). If V
MAX
+ t
60µs
F
.
IL
IL
PUP
to V
to the input high threshold
in the system is close to
OVERDRIVE SPEED
TH
53µs
MIN
9µs
2µs
8µs
7µs
. The actual maximum
CC
power
(undef)
MAX
80µs
26µs
16µs
7µs