DS1372 Maxim, DS1372 Datasheet - Page 3

• Manufacturer Part Number: DS1372
• Description: The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID
• Manufacturer: Maxim

ELECTRICAL CHARACTERISTICS (continued)
(V
CRYSTAL SPECIFICATIONS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement t
Note 11: C
Note 12: The parameter t
Note 13: The DS1372 can detect any single SCL clock held low longer than T
Data Setup Time (Note 10)
Rise Time of SDA and SCL
Signals (Note 11)
Fall Time of SDA and SCL Signals
(Note 11)
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line (Note 11)
I/O Capacitance
SCL Spike Suppresion
Oscillator Stop Flag (OSF) Delay
(Note 12)
Timeout Interval (Note 13)
Nominal Frequency
Capacitive Load
Equivalent Series Resistance
I
CC
2
= 2.4V to 5.5V, T
C, 32-Bit, Binary Counter Clock with 64-Bit ID
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL clocking at maximum frequency = 400kHz.
Specified with I
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
The I
The first clock pulse is generated after this period.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
2.4V ≤ V
can receive a new START condition when SCL is held low for at least T
tion the SDA output is released. The oscillator must be running for this function to work.
PARAMETER
PARAMETER
B
= Total capacitance of one bus line in pF.
2
C minimum operating frequency is imposed by the requirement of timeout period.
CC
_______________________________________________________________________________________
A
≤ V
= -40°C to +85°C, unless otherwise noted.) (Note 1)
CC(MAX)
2
HD:DAT
OSF
C bus inactive, SCL = SDA = V
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
must only be met if the device does not stretch the low period (t
.
T
SYMBOL
SYMBOL
_TIMEOUT
t
t
SU:DAT
SU:STO
C
t
ESR
TSP
C
OSF
C
f
t
t
I/O
O
R
F
B
L
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
MIN
CC
32.768
.
TYP
12.5
CONDITIONS
MAX
50
_TIMEOUT
UNITS
kHz
_TIMEOUT
k
pF
(MIN). The I
R(MAX)
(MAX). Once the part detects this condi-
SU:DAT
LOW
0.1C
0.1C
0.1C
0.1C
+ t
20 +
20 +
20 +
20 +
MIN
100
250
0.6
4.0
25
2
SU:DAT
≥ 250ns must then be met.
) of the SCL signal.
C interface is in reset state and
B
B
B
B
TYP
= 1000 + 250 = 1250ns
100
10
30
IHMIN
of the SCL sig-
MAX
1000
300
300
300
400
35
UNITS
ms
ms
ns
ns
ns
μs
pF
pF
ns
3