DS1372 Maxim, DS1372 Datasheet - Page 7

• Manufacturer Part Number: DS1372
• Description: The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID
• Manufacturer: Maxim

The DS1372 has two additional registers that control
the alarm counter and interrupts: Control Register (07h)
and Status Register (08h).
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped. This bit is clear (logic 0) when power is
first applied.
Bit 6: Alarm Counter Enable (ACE). When set to logic
1, the alarm counter is enabled. If alarm counter seed
register has a nonzero value, the counter runs and sets
the AF bit to 1 when the counter reaches 0. When set to
logic 0, the alarm counter is disabled, and the counter
can be used as RAM. This bit is clear (logic 0) when
power is first applied.
Bit 3: Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin whose fre-
quency is defined by bits RS2 and RS1, according to
Table 2. The oscillator must also be enabled for the
square wave to be output. When the INTCN bit is set to
logic 1, this permits the AF bit in the Status Register to
assert SQW/INT (provided that ACE and AIE are also
enabled) whenever AF = 1. If ACE = 1, the alarm flag is
always set on an alarm condition, regardless of the
state of the INTCN bit. The INTCN bit is set to logic 1
when power is first applied.
Bit #
Name
Reset
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
Special Purpose Registers
_______________________________________________________________________________________
7
0
Control Register (07h)
ACE
6
0
5
0
0
4
0
0
Bits 2 and 1: Rate Select (RS[2:1]). These bits control
the frequency of the square-wave output when the
square wave has been enabled. Table 2 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0: Alarm Interrupt Enable (AIE). When set to a
logic 1, this bit permits the alarm flag (AF) to assert
SQW/INT (when INTCN = 1). The AIE bit is disabled
(logic 0) when power is first applied.
Table 2. Square-Wave/Interrupt Output
Frequencies
Note: When interrupt operation is enabled, the SQW/INT out-
put is the inverse of the AF bit.
INTCN
0
0
0
0
1
INTCN
ACE
3
1
X
X
X
X
1
AIE
X
X
X
X
1
RS2
2
1
RS2
X
0
0
1
1
Control Register (07h)
RS1
RS1
1
1
X
0
1
0
1
32.768kHz
4.096kHz
8.192kHz
SQW/
OUTPUT
Interrupt
1Hz
AIE
0
0
7