DS80C411 Maxim, DS80C411 Datasheet - Page 4

• Manufacturer Part Number: DS80C411
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
External Crystal Frequency
External Clock Oscillator Frequency
ALE Pulse Width
Port 0 Instruction Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instruction In
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
PSEN Low to Address Float
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
CC3
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
= 3.0V to 3.6V, V
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
t
the External Clock Oscillator (XTAL1) Characteristics table.
The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 (
PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid
bus contention.
References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not
for determing absolute signal timing with respect to the external clock.
CLCL
, t
PARAMETER
CLCH
, t
CHCL
CC1
are time periods associated with the internal system clock and are related to the external clock (t
= 1.8V ±10%, T
A
SYMBOL
= -40°C to +85°C.) (Note 1)
1 / t
1 / t
t
t
t
t
t
t
t
t
t
t
t
t
PLPH
AVIV0
AVIV2
AVLL
LLAX
PLAZ
LHLL
LLPL
LLIV
PLIV
PXIX
PXIZ
CLK
CLK
4 of 102
15.0
21.7
MIN
1.7
4.7
3.7
0
75MHz
MAX
14.3
21.0
24.7
8.7
8.3
0
t
CLCL
2t
t
t
t
CHCL
CLCH
CLCH
CLCL
+ t
MIN
DC
16
11
16
11
4
0
VARIABLE CLOCK
CHCL
- 5
- 2
- 3
- 5
- 5
2t
3t
CLCL
CLCL
3t
2t
t
CLCL
CLCL
18.75
18.75
CLCL
MAX
+ t
+ t
37.5
37.5
40
75
0
CLCH
CLCH
- 5
- 19
-18
CLK
- 19
- 22
) as defined in
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns