DS80C411 Maxim, DS80C411 Datasheet - Page 45

• Manufacturer Part Number: DS80C411
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

Table 3. Extended Address Generation
Table 4. Chip-Enable Generation
Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are
Note 2: The default P4CNT.5-3 = 111b setting (4MB accessible per CE) requires only four chip enables in order to access the maximum 24-bit
Note 3: Default condition when the internal ROM is disabled.
Note 4: When the internal ROM is enabled, the default memory map is reconfigured to 2MB per CE, P4CNT.5-3 = 101b, and CE4 to CE7 are
External Data Memory Addressing
Using a similar implementation as was used to expand program memory access, the DS80C410 allows up to 4MB
of data memory access through four peripheral chip enables (PCE). The Port 5 control register (P5CNT; A2h) and
Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of
addressable data memory per peripheral chip enable.
chip enables, along with the maximum memory accessible through each peripheral chip enable for P5CNT, P6CNT
bit settings.
Table 5. Peripheral Chip-Enable Generation
Demultiplexed External Memory Addressing
On power-up or following any reset, the DS80C410 defaults to the traditional 8051 external memory interface, with
the address MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode
requires an external latch to demultiplex the address LSB and data. The DS80C410 provides an external pin (MUX)
that, when pulled high during a power-on reset, demultiplexes the address LSB and data. If demultiplexed mode is
enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,
demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In
some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.
Table 6
modes.
000 (default)
000 (Note 3)
111 (Note 4)
P6CNT.2–0
P5CNT.2–0
110 or 111(default)
P4CNT.5–3
100
101
110
100
101
110
111
needed in order to address the standard 16-bit (0–FFFFh) address range.
(0–FFFFFFh) address range.
enabled, P6CNT.2-0 = 111b.
shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing
000
001
010
011
100
101
PCE3
P5.7
P6.3
CE7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT 6 PIN FUNCTION
P6.5
A21
I/O
I/O
I/O
I/O
I/O
I/O
PCE2
PCE2
P5.6
P6.2
CE6
CE6
I/O
I/O
I/O
I/O
I/O
I/O
P6.4
A20
A20
I/O
I/O
I/O
I/O
I/O
PCE1
PCE1
PCE1
P5.5
P6.1
I/O
I/O
CE5
CE5
CE5
I/O
I/O
P4.7
A19
A19
A19
I/O
I/O
I/O
I/O
PCE0
PCE0
PCE0
PCE0
P5.4
I/O
P6.0
CE4
CE4
CE4
CE4
I/O
P4.6
A18
A18
A18
A18
I/O
I/O
I/O
45 of 102
Table 5
P4.5
A17
A17
A17
A17
A17
I/O
I/O
000 (default)
P6CNT.5–3
111(default)
P4CNT.2–0
001
010
011
100
shows which port pins are converted to peripheral
000
100
101
110
P4.4
A16
A16
A16
A16
A16
A16
I/O
MAX MEMORY ACSESSIBLE per PCE
P4.3
CE3
MAX MEMORY ACCESSIBLE
I/O
I/O
I/O
I/O
PORT 4 PIN FUNCTION
32kB (Note 1)
2MB (Note 4)
4MB (Note 2)
P4.2
CE2
CE2
I/O
I/O
I/O
per CE
128kB
256kB
512kB
1MB
128kB
256kB
512kB
32kB
1MB
P4.1
CE1
CE1
CE1
I/O
I/O
P4.0
CE0
CE0
CE0
CE0
I/O