71M6541F Maxim, 71M6541F Datasheet
71M6541F
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71M6541F Summary of contents
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... Support Shunts • High-Speed Wh/VARh Pulse Outputs with Programmable Width • 32KB Flash, 3KB RAM (71M6541D) • 64KB Flash, 5KB RAM (71M6541F/42F) • 128KB Flash, 5KB RAM (71M6541G/42G) • Four Pulse Outputs with Pulse Count • Four-Quadrant Metering • Digital Temperature Compensation: ...
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Data Sheet 1 Introduction ................................................................................................................................. 10 2 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 14 2.2.2 Input Multiplexer ........................................................................................................ 15 2.2.3 Delay Compensation ................................................................................................. ...
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Fault and Reset Behavior ...................................................................................................... 85 3.3.1 Events at Power-Down .............................................................................................. 85 3.3.2 IC Behavior at Low Battery Voltage ........................................................................... 86 3.3.3 Reset Sequence ........................................................................................................ 86 3.3.4 Watchdog Timer Reset .............................................................................................. 86 3.4 Wake Up Behavior ................................................................................................................ 87 3.4.1 ...
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... Data Sheet 6.1 Absolute Maximum Ratings ................................................................................................. 138 6.2 Recommended External Components ................................................................................. 139 6.3 Recommended Operating Conditions .................................................................................. 139 6.4 Performance Specifications ................................................................................................. 140 6.4.1 Input Logic Levels ................................................................................................... 140 6.4.2 Output Logic Levels ................................................................................................. 140 6.4.3 Battery Monitor ........................................................................................................ 141 6.4.4 Temperature Monitor ............................................................................................... 141 6.4.5 Supply Current ........................................................................................................ 142 6.4.6 V3P3D Switch ......................................................................................................... 143 6.4.7 Internal Power Fault Comparators ........................................................................... 143 6.4.8 2.5 V Voltage Regulator – ...
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Figures Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors) ............................................................... 12 Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01.................................................................. 13 Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors) .................................................................. 13 Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01 ..................................................................... 14 ...
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Data Sheet Tables Table 1. Required CE Code and Settings for Local Sensors ................................................................... 15 Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor ................................................. 16 Table 3: ADC Input Configuration ......................................................................................................... 17 Table 4: ...
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... Table 90: CE Pulse Generation Parameters......................................................................................... 133 Table 91: CE Parameters for Noise Suppression and Code Version..................................................... 134 Table 92: CE Calibration Parameters ................................................................................................... 135 Table 93: Absolute Maximum Ratings .................................................................................................. 138 Table 95: Recommended Operating Conditions ................................................................................... 139 Table 96: Input Logic Levels ................................................................................................................ 140 Table 97: Output Logic Levels ............................................................................................................. 140 Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) ...
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Data Sheet Table 107: LCD Driver Performance Specifications .............................................................................. 145 Table 108: LCD Driver Performance Specifications .............................................................................. 146 Table 109: VREF Performance Specifications ...................................................................................... 148 Table 110. ADC Converter Performance Specifications ....................................................................... 149 Table 111: Pre-Amplifier Performance ...
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IAP IAN IBP VBIAS MUX IBN and PREAMP VREF VA VB* MUX CROSS MUX CTRL CK32 RTCLK (32KHz) XIN Oscillator XOUT 32 KHz 4.9 MHz CK_4X CLOCK GEN CKMPU_2x MUX_SYNC CKCE < 4.9MHz TEST TEST MODE CE CONTROL CKMPU < ...
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... Data Sheet 1 Introduction This data sheet covers the 71M6541D (32KB), 71M6541F (64KB), 71M6541G (128KB), 71M6542F (64KB), and 71M6542G (128KB) fourth generation Teridian energy measurement SoCs. The term “71M654x” is used when discussing a device feature or behavior that is applicable to all four part numbers ...
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Hardware Description 2.1 Hardware Overview The Teridian 71M6541D/F/G and 71M6542F/G single-chip energy meter ICs integrate all primary functional blocks required to implement a solid-state residential electricity meter. Included on the chip are: • An analog front end (AFE) featuring ...
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Data Sheet standards. Temperature-dependent external components such as crystal oscillator, resistive shunts, current transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional ...
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Figure 3 shows the 71M6541D/F/G multiplexer interface with one local and one remote resistive shunt sensor. As seen in Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated with this current channel are ...
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Data Sheet Figure 5 shows the 71M6542F/G multiplexer interface with one local and one remote resistive shunt sensor. As seen in Figure 5, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated ...
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The performance of the IAP-IAN pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8, using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IAP-IAN become the inputs to the 8x ...
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Data Sheet Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor I/O RAM Mnemonic FIR_LEN[1:0] ADC_DIV PLL_FAST MUX_DIV[3:0] MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] RMT_E DIFFA_E DIFFB_E EQU[2:0] CE Code Equations Current Sensor Type Applicable Figure Notes: ...
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For both multiplexer sequences shown in (where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 ...
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Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE ...
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... Selects the ADC input converted during time slot 10. Controls the rate of the ADC and FIR clocks. The number of ADC time slots in each multiplexer frame (maximum = 11). Controls the speed of the PLL and MCK. Determines the number of ADC cycles in the ADC decimation FIR filter. ...
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Data Sheet the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., o 360 ), then routing ...
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V inp V inn CROSS Figure 8: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS (an internal signal), in the A ...
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Data Sheet 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface) 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M654x via a combination of a pulse transformer and a ...
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Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignored if used. The remaining codes are reserved ...
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Data Sheet RST Name Address Default TMUXRB[2:0] 270A[2:0] 000 RMT_RD[15:8] 2602[7:0] RMT_RD[7:0] 2603[7:0] RFLY_DIS 210C[3] RMTB_E 2709[3] Refer to Table 76 starting on page 2.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs ...
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SUM_SAMPS[12:0] supports an accumulation scheme where the incremental energy values from up to SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation interval. The integration time for each energy output is, for example, SUM_SAMPS[12:0]/2520.6 (with MUX_DIV[3:0] = 011, I/O RAM ...
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Data Sheet CK32 MUX_SYNC MUX_STATE CKTEST RTM FLAG RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) ADC TIMING CK32 150 MUX_SYNC MUX STATE S 0 ...
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Pulse Generators The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can be used to output CE status indicators, SAG ...
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... Data Sheet If the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A default, WPULSE and VPULSE are negative pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the maximum negative pulse width T ...
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IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G multiplexer, as seen in Figure 3. In this case, the sample is taken during the second half of the multiplexer cycle and the data ...
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Data Sheet IA 122.07 µs CK32 (32768 Hz) MUX STATE S 0 Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3: 91.5 µs CK32 (32768 Hz) MUX STATE S 0 Figure 15: Samples from Multiplexer Cycle ...
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MPU Core The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant ...
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Data Sheet The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR ...
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An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or ...
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Data Sheet 2.4.3 Generic 80515 Special Function Registers Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed ...
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Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is ...
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Data Sheet SFR SFR Name Address P0 0x80 P1 0x90 P2 0xA0 P3 0xB0 Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR P0 to P3), an output driver ...
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UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. • UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. Several ...
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Data Sheet UART Control Registers: The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON and S1CON shown in Table 19 and Since the TI0, RI0, TI1 and RI1 bits ...
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... (T0 and T1 are the timer gating inputs derived from certain DIO pins, see 2.5.8 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the state, an input should be stable for at least 1 machine cycle. ...
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Data Sheet Table 24: TMOD Register Bit Description (SFR 0x89) Bit Symbol Function Timer/Counter 1 If TMOD[7] is set, external input signal control is enabled for Counter 1. The TMOD[7] Gate TR1 bit in the TCON register ...
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IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 16 shows the device interrupt structure. Referring to Figure 16, interrupt sources ...
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Data Sheet IEN1[2] EX3 IEN1[1] EX2 IEN1[0] – Table 28: The IEN2 Bit Functions (SFR 0x9A) Bit Symbol IEN2[0] ES1 Table 29: TCON Bit Functions (SFR 0x88) Bit Symbol TCON[7] TF1 TCON[6] TR1 TCON[5] TF0 TCON[4] TR0 ...
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IRCON[1] IEX2 IRCON[0] – TF0 and TF1 (Timer 0 and Timer 1 overflow flags) are automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is ...
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Data Sheet External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface. The ...
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Interrupt Enable Name Location EX_SPI 0x2701[7] EX_EEX 0x2700[7] EX_XPULSE 0x2700[6] EX_YPULSE 0x2700[5] 0x2701[6] EX_WPULSE EX_VPULSE 0x2701[5] Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 34: Interrupt Priority Level Groups Group 0 External interrupt ...
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Data Sheet Interrupt Sources and Vectors Table 38 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 46 Table 37: Interrupt Polling ...
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... On-Chip Resources 2.5.1 Physical Memory 2.5.1.1 Flash Memory The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB (71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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The page erase sequence is: • Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). • Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Program Security When enabled, the security feature limits the ICE to global flash erase operations ...
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... The oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC. Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Clock (RTC) for more information ...
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Derived Clock From OSC Crystal MCK Crystal/PLL CKCE MCK CKADC MCK CKMPU MCK CKICE MCK CKOPTMOD MCK CK32 MCK 2.5.4 Real-Time Clock (RTC) 2.5.4.1 RTC General Description The RTC is driven directly by the crystal oscillator and is powered by ...
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... RTC. Setting RTCA_ADJ[6: minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6: maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately: The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the external crystal capacitors ...
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Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is: For example, for a shift of -988 ppm, 4⋅RTC_P + RTC_Q = 262403 = 0x40103. RTC_P = 0x10040, and RTC_Q = 0x03. The default values of ...
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Data Sheet Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right- shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A ...
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For proper operation, the MPU must load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once during ...
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Data Sheet 2.5.5 71M654x Temperature Sensor The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to ...
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Name Location TEMP_BAT 28A0[4] 28B4[6] TEMP_START TEMP_PWR 28A0[6] TEMP_BSEL 28A0[7] TEMP_TEST[1:0] 2500[1:0] STEMP[10:3] 2881[7:0] STEMP[2:0] 2882[7:5] BSENSE[7:0] 2885[7:0] BCURR 2704[3] Refer to the 71M6xxx Data Sheet for information on reading the temperature sensor in the 71M6x01 devices. 2.5.6 71M654x Battery ...
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Data Sheet Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices. 2.5.7 UART and Optical Interface The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both can ...
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UART1_RX 0 UART1_TX 1 DIO5 0 1 OPT_BB 2.5.8 Digital I/O and LCD Segment Drivers 2.5.8.1 General Information The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured as a DIO pin ...
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Data Sheet Value in DIO_Rn[2:0] 5 Note: Resources are selectable only on SEGDIO2 through SEGDIO11 and the PB pin. See Table 48 When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD ...
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Digital I/O for the 71M6541D/F/G A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G. These pins can be categorized as follows: 17 combined SEG/DIO segment pins: SEGDIO4…SEGDIO5 (2 pins) o SEGDIO9…SEGDIO14 (6 ...
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Data Sheet Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G) SEGDIO – – Pin # – – – – Configuration DIO LCD LCD_MAP[23:19] (I/O RAM 0x2409) – – SEG Data Register – ...
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Digital I/O for the 71M6542F/G A total of 55 combined SEG/DIO pins are available for the 71M6542D/F. These pins can be categorized as follows: 35 combined DIO/LCD segment pins: SEGDIO4…SEGDIO5 (2 pins) o SEGDIO9…SEGDIO25 (17 pins) o SEGDIO28…SEGDIO35 (8 ...
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Data Sheet Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) SEGDIO 16 17 Pin # Configuration DIO LCD LCD_MAP[23:16] (I/O RAM 0x2409 SEG Data Register 16 ...
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... A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a maximum LCD voltage that is within twice the supply voltage. The doubler and DAC operate from a trimmed low-power reference. ...
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Data Sheet The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with six back planes, the 6-way multiplexing compresses the number of SEG pins required to ...
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... VLCD voltage and has an output range of 2.5 VDC to 5 VDC. The VLCD voltage is 0 – R/W VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31 Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is limited by V3P3SYS, VBAT, and whether LCD_BSTE is set. Sets the LCD clock frequency (1/T). See definition Figure 21. ...
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Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in ...
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... LCD Drivers (71M6541D/F/G) With a maximum of 35 LCD driver pins available, the 71M6541D/F/G is capable of driving 210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to 26 digits. LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in SEG46 through SEG50 cannot be configured as DIO pins ...
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... Data Sheet LCD Drivers (71M6542F/G) With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving 336 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to 42 digits. LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in for the ...
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Table 60: EECTRL Bits for 2-pin Interface Status Read/ Reset Name Bit Write State 7 ERROR R 6 BUSY R 5 RX_ACK R 4 TX_ACK R 3:0 W 0000 CMD[3:0] The EEPROM interface can also be operated by controlling the ...
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Data Sheet Indicates that EEDATA (SFR 0x9E filled with data from EEPROM Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of ...
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EECTRL Byte Written INT5 not issued Write -- No HiZ SCLK (output) SDATA (output) D7 SDATA output Z (LoZ) BUSY (bit) Figure 25: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written Write -- With HiZ and WFR SCLK (output) ...
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Data Sheet When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR 0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if ...
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SERIAL READ 16 bit Address (From Host) SPI_CSZ 0 15 (From Host) SPI_CK (From Host) SPI_DI A0 A15 A14 (From 654x) SPI_DO SERIAL WRITE 16 bit Address (From Host) SPI_CSZ 0 15 (From Host) SPI_CK A14 (From ...
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Data Sheet Name Location Rst 2701[7] 0 EX_SPI SPI_CMD SFR FD[7:0] – SPI_E 270C[4] 1 IE_SPI SFR F8[7] 0 270C[3] 0 SPI_SAFE 2708[7:0] 0 SPI_STAT 76 Table 64: SPI Registers Wk Dir Description 0 R/W SPI interrupt ...
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SPI Flash Mode (SFM) In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6541D/F/G and 71M6542F/G support an SPI Flash Mode (SFM) which facilitates initial programming of the flash memory. When in SFM ...
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Data Sheet SFM details The following occurs upon entering SFM. • The CE is disabled. • The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be ...
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The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product development cycle or in the production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides higher precision ...
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Data Sheet 3 Functional Description 3.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy ...
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Battery Modes Shortly after system power (V3P3SYS) is applied, the part is in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the ...
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Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: • Wake-up timer timeout. • Pushbutton (PB) is activated. • A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) ...
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... TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT output set value • TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set value • CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum • TEMP_PER[2: (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s • ...
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Data Sheet 3.2.3 SLP Mode When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN ...
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Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A ...
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Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at ...
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There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT can be disabled by raising the ICE_E pin to 3.3 VDC. In normal operation, the WDT is reset by periodically writing a one ...
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Data Sheet Wake Enable Name Location Name Always Enabled WF_RST Always Enabled WF_RSTBIT Always Enabled WF_ERST Always Enabled WF_OVF Always Enabled WF_CSTART Always Enabled WF_BADVDD † 71M6542F/G only. *This pin is sampled every 2 ms and must ...
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Name Location RST 28B3[2] 0 EW_DIO4 EW_DIO52 28B3[1] 0 EW_DIO55 28B3[0] 0 WAKE_ARM 28B2[5] 0 28B3[3] 0 EW_PB EW_RX 28B3[4] 0 WF_DIO4 28B1[2] 0 WF_DIO52 28B1[1] 0 WF_DIO55 28B1[0] 0 WF_TMR 28B1[5] 0 WF_PB 28B1[3] 0 WF_RX 28B1[4] 0 WF_RST ...
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Data Sheet Flag WF_TMR Timer expiration WF_PB PB pin high level WF_RX Either edge RX pin WF_DIO4 SEGDIO4 rising edge WF_DIO52 SEGDIO52 high level (71M6542F/G only) If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high ...
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Data Flow and MPU/CE Communication The data flow between the Compute Engine (CE) and the MPU is shown in application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, etc., performing calculations ...
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Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are ...
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Using Local Sensors Figure 35 shows a 71M6541D/F/G configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a ...
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Data Sheet 4.4 71M6541D/F/G Using 71M6x01and Current Shunts Figure 36 shows a typical connection for one isolated and one non-isolated shunt sensor, using the 71M6x01 Isolated Sensor Interface. This configuration implements a single-phase measurement with tamper-detection using ...
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Using Local Sensors Figure 38 shows a 71M6542F/G configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a ...
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Data Sheet 4.6 71M6542F/G Using 71M6x01 and Current Shunts Figure 38 shows a typical two-phase connection for the 71M6542F/G using one isolated and one non- isolated sensor. For best performance, the IAP-IAN current sensor input is configured ...
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... The above calculation implies that both the voltage and the current measurements are individually subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately ± ...
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Data Sheet See 4.7.3 and 4.7.4 below for further temperature compensation details. 4.7.3 Temperature Compensation for VREF with Local Sensors This section discusses metrology temperature compensation for the meter designs where local sensors are used, as shown ...
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To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2 coefficients are set with values that match the expected ...
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Data Sheet compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this channel. • GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x VREF. The designer may optionally add ...
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Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2/SDCK and SEGDIO3/SDATA, as described in 4.10 UART0 (TX/RX) The UART0 RX pin should be pulled down kΩ resistor and ...
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Data Sheet If operation in BRN mode is desired, the external components should be connected to V3P3D. However recommended to limit the current to a few mA. 71M654x OPT_RX OPT_TX Figure 41: Connection for Optical ...
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V3P3D 62 Ω 62 Ω 62 Ω Figure 43: External Components for the Emulator Interface Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet LCD Segments (optional) 71M654x ICE_E E_RST E_RXT E_TCLK 103 ...
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... The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin. Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts have XIN and XOUT shielded from each other and from LCD and digital signals ...
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Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 74 and Table 75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing ...
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Data Sheet Name Addr Bit 7 LCD_MAP5 2015 LCD_MAP4 2016 LCD_MAP3 2017 LCD_MAP2 2018 LCD_MAP1 2019 LCD_MAP0 201A DIO_R5 201B U DIO_R4 201C U DIO_R3 201D U DIO_R2 201E U DIO_R1 201F U DIO_R0 2020 U DIO0 ...
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Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Name Addr Bit 7 CE and ADC MUX5 2100 MUX4 ...
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Data Sheet Name Addr Bit 7 LCD_MAP4 2407 LCD_MAP3 2408 LCD_MAP2 2409 LCD_MAP1 240A LCD_MAP0 240B LCD4 240C U LCD_DAC 240D U SEGDIO0 2410 U … … U SEGDIO15 241F U SEGDIO16 2420 U … … U ...
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Name Addr Bit 7 TMUX2 2503 U RTC1 2504 U 71M6x01 Interface REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 EX_EEX EX_XPULSE INT2_E 2701 EX_SPI EX_WPULSE SECURE 2702 Analog0 2704 VREF_CAL VREF_DIS VERSION 2706 INTBITS 2707 U FLAG0 SFR E8 IE_EEX ...
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Data Sheet Name Addr Bit 7 RTC2 2892 RTC3 2893 U RTC4 2894 U RTC5 2895 U RTC6 2896 U RTC7 2897 U RTC8 2898 U RTC9 2899 RTC10 289B U RTC11 289C RTC12 289D RTC13 289E ...
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I/O RAM Map – Alphabetical Order Table 76 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored ...
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Data Sheet Name Location CHOPR[1:0] 2709[7:6] DIFFA_E 210C[4] 210C[5] DIFFB_E DIO_R2[2:0] 2455[2:0] DIO_R3[2:0] 2455[6:4] 2454[2:0] DIO_R4[2:0] 2454[6:4] DIO_R5[2:0] DIO_R6[2:0] 2453[2:0] DIO_R7[2:0] 2453[6:4] DIO_R8[2:0] 2452[2:0] DIO_R9[2:0] 2452[6:4] DIO_R10[2:0] 2451[2:0] 2451[6:4] DIO_R11[2:0] 2450[2:0] DIO_RPB[2:0] DIO_DIR[15:12] SFR B0[7:4] DIO_DIR[11:8] SFR ...
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Name Location DIO_PV 2457[6] DIO_PW 2457[7] DIO_PX 2458[7] 2458[6] DIO_PY EEDATA[7:0] SFR 9E SFR 9F EECTRL[7:0] EQU[2:0] 2106[7:5] Rev 2 Rst Wk Dir Description R/W Causes VARPULSE to be output on pin SEGDIO1, if LCD_MAP[ – 0 ...
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Data Sheet Name Location EX_XFER 2700[0] EX_RTC1S 2700[1] EX_RTC1M 2700[2] EX_RTCT 2700[3] EX_SPI 2701[7] EX_EEX 2700[7] EX_XPULSE 2700[6] EX_YPULSE 2700[5] EX_WPULSE 2701[6] 2701[5] EX_VPULSE EW_DIO4 28B3[2] EW_DIO52 28B3[1] EW_DIO55 28B3[0] EW_PB 28B3[3] 28B3[4] EW_RX FIR_LEN[1:0] 210C[2:1] 114 ...
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Name Location SFR 94[7:0] FLSH_ERASE[7:0] FLSH_MEEN SFR B2[1] SFR B2[3] FLSH_PEND FLSH_PGADR[5:0] SFR B7[7:2] FLSH_PSTWR SFR B2[2] FLSH_PWE SFR B2[0] FLSH_RDE 2702[2] FLSH_UNLOCK[3:0] 2702[7:4] FLSH_WRE 2702[1] Rev 2 Rst Wk Dir Description Flash Erase Initiate FLSH_ERASE is used to initiate ...
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... The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of 2 The VLCD voltage is 0 – R/W VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31 Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1. Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are 0 – R/W ground as are the COM and SEG outputs if their LCD_MAP bit is 1 ...
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Name Location LCD_MAP[55:48] 2405[7:0] LCD_MAP[47:40] 2406[7:0] LCD_MAP[39:32] 2407[7:0] LCD_MAP[31:24] 2408[7:0] LCD_MAP[23:16] 2409[7:0] LCD_MAP[15:8] 240A[7:0] LCD_MAP[7:0] 240B[7:0] LCD_MODE[2:0] 2400[6:4] LCD_ON 240C[0] LCD_BLANK 240C[1] LCD_ONLY 28B2[6] LCD_RST 240C[2] LCD_SEG0[5:0] 2410[5: 241F[5:0] LCD_SEG15[5:0] LCD_SEGDIO16[5:0] 2420[5: 243D[5:0] LCD_SEGDIO45[5:0] LCD_SEG46[5:0] to ...
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... R/W which time the strobe is cleared and LKPADDR[6:0] is incremented if the LKPAUTOI bit is set. MPU clock rate is: MPU Rate = MCK Rate * 2 The maximum value for MPU_DIV[2: Based on the default values R/W the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 6.29 MHz / 4 = 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAS ...
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... Rst Wk Dir Description MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The 0 0 R/W maximum number of time slots is 11. Configures the input of the optical port DIO pin to allow bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to 0 – R/W 2.5.7 UART and Optical Interface (Third UART)” ...
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... R 19.66 MHz (XTAL * 600 6.29 MHz (XTAL * 192) PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is (2*PLS_MAXWIDTH[7:0] + 1)* R/W units of CK_FIR clock cycles. If PLS_INTERVAL[7: PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the output pulses have 50% duty cycle. See PLS_INTERVAL[7:0] determines the interval time between pulses ...
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Name Location RMT_E 2709[3] RMT_RD[15:8] 2602[7:0] RMT_RD[7:0] 2603[7:0] RTC_FAIL 2890[4] RTC_P[16:14] 289B[2:0] 289C[7:0] RTC_P[13:6] RTC_P[5:0] 289D[7:2] RTC_Q[1:0] 289D[1:0] RTC_RD 2890[6] 2892[7:0] RTC_SBSC[7:0] RTC_TMIN[5:0] 289E[5:0] 289F[4:0] RTC_THR[4:0] 2890[7] RTC_WR RTC_SEC[5:0] 2893[5:0] RTC_MIN[5:0] 2894[5:0] RTC_HR[4:0] 2895[4:0] RTC_DAY[2:0] 2896[2:0] 2897[4:0] RTC_DATE[4:0] RTC_MO[3:0] 2898[3:0] ...
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... R The result of the temperature measurement. – – R The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value 0 0 R/W is 8191 cycles. Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are locked out while it is one. Write duration could be as long as ...
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Name Location TEMP_22[10:8] 230A[2:0] TEMP_22[7:0] 230B[7:0] TEMP_BAT 28A0[4] TEMP_BSEL 28A0[7] TBYTE_BUSY 28A0[3] 28A0[2:0] TEMP_PER[2:0] TEMP_PWR 28A0[6] TEMP_START 28B4[6] 2502[5:0] TMUX[5:0] TMUX2[4:0] 2503[4:0] TMUXRA[2:0] 270A[2:0] VERSION[7:0] 2706[7:0] VREF_CAL 2704[7] VREF_DIS 2704[6] Rev 2 Rst Wk Dir Description 0 – R Storage ...
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Data Sheet Name Location VSTAT[2:0] SFR F9[2:0] WAKE_ARM 28B2[5] 2880[7:0] WAKE_TMR[7:0] WD_RST 28B4[7] WF_DIO4 28B1[2] WF_DIO52 28B1[1] WF_DIO55 28B1[0] WF_TMR 28B1[5] 28B1[3] WF_PB WF_RX 28B1[4] WF_CSTART 28B0[7] WF_RST 28B0[6] 28B0[5] WF_RSTBIT WF_OVF 28B0[4] WF_ERST 28B0[3] WF_BADVDD 28B0[2] ...
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CE Interface Description 5.3.1 CE Program The CE performs the precision computations necessary to accurately measure energy. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All ...
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Data Sheet The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are essential to the function of the CE are stored in I/O RAM (see details). 5.3.4 Environment Before starting the CE using the ...
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CE Front End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading addresses 0-3, 9 and 10 (decimal) shown in Table 79. The MUX_SEL column in Table 79 example, if differential mode ...
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Data Sheet status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in CESTATUS is shown in Table 81. Table 81: CESTATUS (CE RAM 0x80) Bit Definitions CESTATUS Name bit 31:4 Not ...
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EXT_PULSE 4:2 Reserved 1 PULSE_FAST 0 PULSE_SLOW The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag ...
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Data Sheet When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They ...
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Instantaneous Energy Measurement Variables IxSQSUM_X and VxSQSUM (see acquired during the last accumulation interval. Table 87: CE Energy Measurement Variables (with Local Sensors) CE Name Address The sum of squared current samples from each 0x8C I0SQSUM_X element. 0x8D I1SQSUM_X ...
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... See 2.3.6.2 VPULSE and WPULSE The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero attempted to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without exhibiting any rollover characteristics ...
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... SUM_SAMPS[12:0] (CE RAM 0x23) ACC See Table 83 for the definition of X. The default value yields 1.0 Wh/pulse for VMAX = 600 V and IMAX = 208 A. The maximum value for WRATE is 32,768 (2 Scale factor for VAR measurement. SUM_SAMPS (N ). ACC Wh pulse (WPULSE) generator input to be updated by the MPU when using external pulse generation ...
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Data Sheet 5.3.10 Other CE Parameters Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 91: CE Parameters for Noise Suppression and Code Version CE Name Default Address ...
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CE Calibration Parameters Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Name Default Address 0x10 CAL_IA 16384 0x11 CAL_VA 16384 0x13 16384 CAL_IB † 0x14 16384 CAL_VB 0x12 0 PHADJ_A 0x15 ...
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Data Sheet 5.3.12 CE Flow Diagrams Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sag detection, scaling and the processing of meter equations. Figure ...
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W0 W1 VAR0 VAR1 SQUARE Figure 46: CE Data Flow: Squaring and Summation Stages Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet SUM Σ Σ Σ Σ SUM_SAMPS=2520 SUM I0SQ Σ V0SQ Σ 2 ...
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... Absolute Maximum Ratings Table 93 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (see Recommended Operating Conditions) is not implied ...
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Solder temperature – 10 second duration ESD stress on all pins 6.2 Recommended External Components Table 94: Recommended External Components Name From To C1 V3P3A GNDA C2 V3P3D GNDD CSYS V3P3SYS GNDD CVDD VDD GNDD CVLCD VLCD GNDD XTAL XIN ...
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Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Parameter 1 Digital high-level input voltage 1 Digital low-level input voltage , V Input pullup current E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs ...
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Battery Monitor Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) Parameter BV: Battery Voltage (definition) Measurement Error BV ⋅ − 100 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied ...
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... LCD_VMODE[1:0]=3, also see note 2 LCD_VMODE[1:0]=2, also see note 3 LCD_VMODE[1:0]=1, also see note 3 LCD_VMODE[1:0]=0, also see note 3 SLP Mode LCD_VMODE[1:0]=2, also see note 2 ≤ 25 ° °C A Same as I1, except write Flash at maximum rate, CE_E=0, ADC_E=0. Min Typ Max Unit 5.5 6.7 mA 2.6 3 ...
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V3P3D Switch Table 101: V3P3D Switch Performance Specifications Parameter On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D V3P3D I , MSN OH V3P3D I , BRN OH 6.4.7 Internal Power Fault Comparators Table 102. Internal ...
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... V2P5 load regulation Voltage Overhead 2V − VBAT-VDD 6.4.10 Crystal Oscillator Measurement conditions: Crystal disconnected, test load of 200 pF/100 kΩ between XOUT and GNDD. Table 105: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal XIN to XOUT Capacitance (see note 1) Capacitance change on XOUT Notes: 1. ...
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LCD Drivers Table 107: LCD Driver Performance Specifications PARAMETER VLCD=3.3, all LCD map bits=0 VLCD Current VLCD=5.0, all LCD map bits=0 (see Notes Notes: 1. These specifications apply to all COM and SEG pins. 2. VLCD ...
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... The above equations describe the nominal value of VLCD for a specific LCD_DAC value. The specifications below list the maximum deviation between actual VLCD and VLCDnom. Note that when VCC and boost are insufficient, the LCD DAC will not reach its target value and a large negative error will occur ...
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Parameter LCD_DAC Error. VLCD-VLCDnom DAC=12, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom Zero Scale, ...
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Data Sheet 6.4.14 VREF Table 109 shows the performance specifications for the ADC reference voltage (VREF). Table 109: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF output voltage, VREF(22) VREF output impedance VREF power supply sensitivity ...
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ADC Converter Table 110. ADC Converter Performance Specifications Parameter Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk Vcrosstalk ∠ − ∠ cos( Vin Vcrosstalk Vin (see note 1) Input Impedance, no pre-amp DC Gain ...
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Data Sheet Notes: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include ...
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Timing Specifications 6.5.1 Flash Memory Table 112: Flash Memory Timing Specifications Parameter Flash write cycles Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 SPI ...
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Data Sheet 6.5.4 RESET Pin Parameter Reset pulse width Reset pulse fall time (see note 1) Notes: 1. Guaranteed by design; not production tested. 6.5.5 RTC Parameter Range for date 152 Table 115: RESET Pin Timing Condition ...
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Package Outline Drawings 6.6.1 64-Pin LQFP Outline Package Drawing 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. Figure 47: 64-pin LQFP Package Outline Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 0.00 ...
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Data Sheet 6.6.2 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 48: 100-pin LQFP Package Outline 154 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 ...
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... The first four digits to the left are the year and week of manufacture as YYWW. In this example, the date code is 1101 which represents year 2011, week 1. The last four characters (i.e., 24TK) are reserved for Maxim internal use only. 445AP A five character lot code ...
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... SEGDIO24 12 SEGDIO23 13 SEGDIO22 14 SEGDIO21 15 SEGDIO20 16 SEGDIO19 Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package) 156 Teridian 42 41 71M6541D 40 71M6541F XIN VBAT_RTC VBAT V3P3SYS IBP IBN GNDD V3P3D VDD ICE_E E_RXTX/SEG48 E_TCLK/SEG49 E_RST/SEG50 RX TX OPT_TX/SEGDIO51 Rev 2 ...
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LQFP-100 Package Pinout 1 SPI_DI/SEGDIO38 SPI_DO/SEGDIO37 2 SPI_CSZ/SEGDIO36 3 SEGDIO35 4 SEGDIO34 5 SEGDIO33 6 SEGDIO32 7 SEGDIO31 8 SEGDIO30 9 SEGDIO29 10 SEGDIO28 11 COM0 12 COM1 13 COM2 14 COM3 15 SEGDIO27/COM4 16 SEGDIO26/COM5 17 SEGDIO25 ...
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Data Sheet 6.9 Pin Descriptions 6.9.1 Power and Ground Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under . Pin Pin ...
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Analog Pins Pin Pin Name Type Circuit Description (64 pin) (100-pin IAP IAN 44 68 IBP IBN † VREF 48 75 XIN 49 76 XOUT ...
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Data Sheet 6.9.3 Digital Pins Table 121 lists the digital pins. Pin types Power Output Input, I/O = Input/Output, N connect. The circuit number denotes the equivalent circuit, as ...
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Pin Pin Name (64-pin) (100-pin ICE_E 60 92 TMUXOUT/SEG47 61 93 TMUX2OUT/SEG46 59 91 RESET TEST 26, 40, 48, 49, 50, 63, 64, 65 66, ...
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Data Sheet 6.9.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input ...
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... KB reel 64 KB bulk tape and 64 KB reel 128 KB bulk tape and 128 KB reel Package Order Number Marking 71M6541D-IGT/F 71M6541D-IGT 71M6541D-IGTR/F 71M6541D-IGT 71M6541F-IGT/F 71M6541F-IGT 71M6541F-IGTR/F 71M6541F-IGT 71M6541G-IGT/F 71M6541G-IGT 71M6541G-IGTR/F 71M6541G-IGT 71M6542F-IGT/F 71M6542F-IGT 71M6542F-IGTR/F 71M6542F-IGT 71M6542G-IGT/F 71M6542G-IGT 71M6542G-IGTR/F 71M6542G-IGT 163 ...
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Data Sheet Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC ...
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Appendix B: Revision History REVISION REVISION NUMBER DATE 1.0 3/11 Initial release Removed the information about 18mW typ consumption at 3.3V in sleep mode from the Features section 1.1 4/11 Updated the Temperature Measurement Equation and Temperature Error parameters in ...
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... Data Sheet Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time ...