71M6541F Maxim, 71M6541F Datasheet - Page 87

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

described in
by a wake-up timer timeout, when the pushbutton (PB) input is high, a high level on SEGDIO4,
SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins.
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition.
Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.
The wake enable and flag bits are also shown in
the MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the
part is already awake.
Table 71
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wake-up is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicate that
system power is stable.
There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT
can be disabled by raising the ICE_E pin to 3.3 VDC.
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit (I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode, and
when ICE_E = 1.
3.4
As described above, the part always wakes-up in MSN mode when system power is restored. As
3.4.1 Wake on Hardware Events
The following pin signal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F/G
only), or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See
details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52
(71M6542F/G only), and SEGDIO55 pins must be configured as DIO inputs and their wake enable (EW_x
bits) must be set. In SLP and LCD modes, the MPU is held in reset and cannot poll pins or react to
interrupts. When one of the hardware wake events occurs, the internal WAKE signal rises and within
three CK32 cycles the MPU begins to execute. The MPU can determine which one of the pins
awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52 (71M6542F/G only), or
WF_DIO55 flags (see
Rev 2
EW_DIO52†
WAKE_ARM
EW_DIO55
EW_DIO4
EW_PB
EW_RX
Name
Wake Enable
Wake Up Behavior
lists the events that clear the WF flags.
Table 69
3.2 Battery
Location
28B2[5]
28B3[3]
28B3[4]
28B3[2]
28B3[1]
28B3[0]
shows which pins are equipped with de-bounce circuitry.
Table
Modes, transitions from both LCD and SLP mode to BRN mode can be initiated
69).
WF_DIO52
WF_DIO55
WF_DIO4
WF_TMR
WF_PB
WF_RX
Name
Table 69: Wake Enables and Flag Bits
Wake Flag
Location
28B1[5]
28B1[3]
28B1[4]
28B1[2]
28B1[1]
28B1[0]
Table
69. The wake flag bits are set by hardware when
De-bounce Description
71M6541D/F/G and 71M6542F/G Data Sheet
2 µs
2 µs
Yes
Yes
Yes
No
Wake on Timer.
Wake on PB*.
Wake on either edge of RX.
Wake on SEGDIO4.
Wake on SEGDIO52*.
OPT_RXDIS = 1: Wake on DIO55*
with 64 ms de-bounce.
OPT_RXDIS = 0: Wake on either
Table
Table 69
69, each of these
for de-bounce
87