71M6541F Maxim, 71M6541F Datasheet - Page 114

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6541D/F/G and 71M6542F/G Data Sheet
114
Name
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
EW_DIO4
EW_DIO52
EW_DIO55
EW_PB
EW_RX
FIR_LEN[1:0]
210C[2:1]
Location
28B3[2]
28B3[1]
28B3[0]
28B3[3]
28B3[4]
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
Rst Wk Dir
0
0
0
0
0
0
0
0
–
–
–
–
–
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC,
etc. The bits are set by hardware and cannot be set by writing a 1. The bits
are reset by writing 0. Note that if one of these interrupts is to enabled, its
corresponding 8051 EX enable bit must also be set. See
details.
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake
the part. This bit has no effect unless DIO4 is configured as a digital input.
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to
wake the part. This bit has no effect unless SEGDIO52 is configured as a
digital input.
The SEGDIO52 pin is only available in the 71M6542F/G.
Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 rising to
wake the part. This bit has no effect unless SEGDIO55 is configured as a
digital input.
Connects PB to the WAKE logic and permits PB rising to wake the part. PB
is always configured as an input.
Connects RX to the WAKE logic and permits RX rising to wake the part. See
the WAKE description on page 87 for de-bounce issues.
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
PLL_FAST = 0:
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting.
Refer to
6.4.15 ADC Converter
FIR_LEN[1:0]
FIR_LEN[1:0]
00
01
10
00
01
10
on page 149.
ADC Cycles
ADC Cycles
Not Allowed
141
288
384
135
276
2.4.8
Interrupts
for
Rev 2