EL4583CS Intersil, EL4583CS Datasheet - Page 9

• Manufacturer Part Number: EL4583CS
• Description: IC VIDEO SYNC SEPARATOR 16-SOIC
• Manufacturer: Intersil
• Type: Synchronous Separatorr

Specifications of EL4583CS

• Applications: Multimedia Displays, Test Equipment
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The signal is processed through an active 3 pole filter (F1)
designed for minimum ripple with constant phase delay. The
filter attenuates the color burst by 12dB and eliminates fast
transient spikes without sync crushing. An external filter is
not necessary. The filter also amplifies the video signal by
6dB to improve the detection accuracy. The filter cut-off
frequency is controlled by an external resistor from pin 1 to
ground.
Internal reference voltages (block V
to supply voltage variation are derived on the chip.
Reference V
voltage of 1.7V nominal. Consequently, it can be seen that
the external resistance R
reference current I
about 6kΩ, much less than R
functions on the chip are referenced to I
excellent supply voltage rejection.
To improve noise immunity, the output of the 3 pole filter is
brought out to pin 7. It is recommended to AC couple the
output to pin 8, the video input pin. In case of strong clean
video signal, the video input pin, pin 8, can be driven by the
signal directly.
Comparator C2 on the input to the sample and hold block
(S/H) compares the leading and trailing edges of the sync.
pulse with a threshold voltage V
fixed level above the clamp voltage V
initiates the timing one-shots for gating the sample and hold
circuits. The sample of the sync tip is delayed by 0.8µs to
enable the actual sample of 2µs to be taken on the optimum
section of the sync. pulse tip. The acquisition time of the
circuit is about three horizontal lines. The double poly CMOS
technology enables long time constants to be achieved with
small high quality on-chip capacitors. The back porch
voltage is similarly derived from the trailing edge of sync,
which also serves to cut off the tip sample if the gate time
exceeds the tip period. Note that the sample and hold gating
times will track R
The 50% level of the sync tip is derived through the resistor
divider R1 and R2, from the sample and held voltages V
and V
This comparator has built in hysteresis to avoid false
triggering. The output of C2 is a digital 5V signal which feeds
the C/S output buffer B1, the vertical, back porch and
odd/even functions.
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BP
and applied to the plus input of comparator C1.
R4
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with op-amp A2 forces pin 12 to a reference
SET
TR
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
. The internal resistance R3 is only
through I
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SET
SET
will determine the value of the
9
OT
R2
. All the internal timing
.
which is referenced at a
REF
R1
) with high immunity
TR
. The output of C2
and have
TIP
EL4583
The vertical circuit senses C/S edges and initiates an
integrator which is reset by the shorter horizontal sync
pulses but times out with the longer vertical sync. pulse
widths. The internal timing circuits are referenced to I
V
timing current. The vertical output pulse is started on the first
serration pulse in the vertical interval and is then self-timed
out. In the absence of a serration pulse, an internal timer will
default the start of vertical.
The horizontal circuit senses C/S edges and produces the
true horizontal pulses of nominal width 5µs. The leading
edge is triggered from the leading edge of the input H sync,
with the same prop. delay as composite sync. The half line
pulses present in the input signal during vertical blanking are
removed with an internal 2H eliminator circuit. The 2H
eliminator initiates a time out period after a horizontal pulse
is generated. The time out period is a function of I
is set by R
The back porch is triggered from the sync tip trailing edge
and initiates a one-shot pulse. The period of this pulse is
again a function of I
set by RESET.
The odd/even circuit (O/E) tracks the relationship of the
horizontal pulses to the leading edge of the vertical output
and will switch on every field at the start of vertical. Pin 13 is
high during an odd field.
Loss of video signal can be detected by monitoring the No
Signal Detect Output pin 10. The VTIP voltage held by the
sample and hold is compared with a voltage level set by R
on pin 2. Pin 10 output goes high when the VTIP falls below
R
VTIP voltage is also passed through an amplifier with gain of
2 and buffed to pin 9. This provides an indication of signal
strength. This signal (Level Output) can be used for AGC
applications.
R3
LV
, the time-out period being inversely proportional to the
set value.
SET
.
OT
and will therefore track the scan rate
November 12, 2010
OT
OT
which
FN7173.3
and
LV