ISL98001CQZ-170 Intersil, ISL98001CQZ-170 Datasheet - Page 13

• Manufacturer Part Number: ISL98001CQZ-170
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-170

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x05
0x06
0x07
0x08
ADDRESS
Input configuration (0x00)
Red Gain (0x55)
Green Gain (0x55)
Blue Gain (0x55)
REGISTER (DEFAULT VALUE)
(Continued)
13
BIT(S)
7:0
7:0
7:0
0
1
2
3
4
5
6
7
ISL98001
Channel Select
Input Coupling
RGB/YPbPr
Sync Type
Composite Sync
Source
COAST CLAMP
enable
Sync Mask Disable
HSYNC
Disable
Red Gain
Green Gain
Blue Gain
FUNCTION NAME
OUT
Mask
0: VGA1
1: VGA2
0: AC coupled (positive input connected to clamp DAC
during clamp time, negative input disconnected from
outside pad and always internally tied to appropriate
clamp DAC).
1: DC coupled (+ and - inputs are brought to pads and
never connected to clamp DACs). Analog clamp
signal is turned off in this mode.
0: RGB inputs
Base ABLC target code = 0x00 for R, G, and B)
1: YPbPr inputs
Base ABLC target code = 0x00 for G (Y)
Base ABLC target code = 0x80 for R (Pr) and B (Pb)
0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
0: SOG
1: HSYNC
Note: If Sync Type = 0, the multiplexer will pass
HSYNC
0: DC restore clamping and ABLC suspended during
COAST.
1: DC restore clamping and ABLC continue during
COAST.
0: Interval between HSYNC pulses masked
(preventing PLL from seeing Macrovision and any
spurious glitches).
1: Interval between HSYNC pulses not masked
(Macrovision will cause PLL to lose lock).
0: HSYNC
sync glitches on incoming SYNC are stripped from
HSYNC
1: HSYNC
sync glitches on incoming SYNC appear on
HSYNC
If Sync Mask Disable = 1, HSYNC
Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x00: gain = 0.5V/V
(1.4V
0x55: gain = 1.0V/V
(0.7V
0xFF: gain = 2.0V/V
(0.35V
P-P
P-P
P-P
IN
IN
OUT
OUT
input = full range of ADC)
input = full range of ADC)
OUT
IN
OUT
regardless of the state of this bit.
input = full range of ADC)
).
).
signal is not masked (any Macrovision,
signal is masked (any Macrovision,
DESCRIPTION
OUT
September 21, 2010
is not masked.
FN6148.5