LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 18

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ADD
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
Name
Output Frame Lookup
– PLL2 Vsync Code
Output Frame Lookup
– PLL3 Vsync Code
Reserved
PLL1 Advanced
Control
PLL1 Advanced
Control FastLock
Delay
PLL1 Advanced
Control
Fastlock CP Current
PLL1 Advanced
Control
Charge Pump Current
PLL1 Advanced
Control
R Counter MSB
PLL1 Advanced
Control
R Counter LSB
Bits
7:4
3:0
7:4
3:0
7:0
7:5
4
3
2
1
0
7:4
3:0
4:0
4:0
7:2
1:0
7:0
Field
RSVD
PLL2 Vsync Code
RSVD
PLL3 Vsync Code
RSVD
RSVD
PLL1_DIV
RSVD
PLL1 Input Mode
RSVD
FastLock
RSVD
FastLock Delay
FastLock Charge
Pump Current
PLL1 Charge Pump
Current
RSVD
MSB
LSB
18
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0101
0110
0
0
1
0000
11111
01000
00
0x01
Description
Reserved
Whenever PLL2_FORMAT (address 7) is
written, this field is updated with the
appropriate Vsync code. If any custom
changes are made the device will set this field
to 4’d14 (0x0E) to so indicate.
Reserved
Whenever PLL3_FORMAT (address 8) is
written, this field is updated with the
appropriate Vsync code. If any custom
changes are made the device will set this field
to 4’d14 (Ox0E) to so indicate.
Reserved
Reserved
0 = Divide by 1 (Output is 27 MHz)
1 = Divide by 2 (Output is 13.5 MHz)
Reserved
Directly controls the mode of the PLL1 input
buffer.
0 = Single Ended
1 = Differential
Reserved
This bit enables ICP1_FAST (address 0x27)
to be used during locking.
0 = FastLock disabled
1 = FastLock enabled
Reserved
Sets the amount of time that PLL1_Lock must
be asserted before the PLL1 Charge pump
current is reduced from the ICP1_Fast value
to the ICP1 value. The time delay is specified
in units of half seconds. Delay =
FastlockDelay*0.5 Seconds. Valid values are
from 0 to 10. Values from 11 to 15 are
reserved.
This field specifies the charge pump current
to drive when FastLock is active. Charge
pump current is equal to 34.375 µA * register
value
This field defines the charge pump current
used when FastLock is not active. Charge
pump current is equal to 34.375 µA * register
value
Reserved
The two LSBs of Register 0x29 along with the
eight bits of Register 0x2A form a ten bit word
which comprises the R divider for PLL1. This
register is internally written based on the
input format and when AutoFormatDetect is
enabled, these registers are read only.