ISL98001CQZ-210 Intersil, ISL98001CQZ-210 Datasheet - Page 15

• Manufacturer Part Number: ISL98001CQZ-210
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-210

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x13
0x14
0x15
0x16
0x17
ADDRESS
PLL Misc (0x04)
DC Restore and ABLC starting pixel MSB
(0x00)
DC Restore and ABLC starting pixel LSB
(0x03)
DC Restore Clamp Width
(0x10)
ABLC Configuration (0x40)
REGISTER (DEFAULT VALUE)
(Continued)
15
BIT(S)
5:4
4:0
7:0
7:0
3:2
6:4
0
1
2
3
6
7
0
1
7
ISL98001
PLL Lock Edge
HSYNC1
PLL Lock Edge
HSYNC2
Reserved
CLKINV
Disable
CLKINV
Function
XCLK
Disable XCLK
DC Restore and
ABLC starting
pixel (MSB)
DC Restore and
ABLC starting
pixel (LSB)
DC Restore clamp
width (pixels)
ABLC disable
Reserved
ABLC pixel width
ABLC bandwidth
Reserved
FUNCTION NAME
OUT
IN
IN
Frequency 0: XCLK
Pin
Pin
OUT
0: Lock on trailing edge of HSYNC1 (default)
1: Lock on leading edge of HSYNC1
0: Lock on trailing edge of HSYNC2 (default)
1: Lock on leading edge of HSYNC2
Set to 0
0: CLKINV
1: CLKINV
00: CLKINV (default)
01: External CLAMP (See Note)
10: External COAST
11: External PIXCLK
Note: the CLAMP pulse is used to
- perform a DC restore (if enabled)
- start the ABLC function (if enabled), and
- update the data to the Offset DACs (always).
In the default internal CLAMP mode, the ISL98001
automatically generates the CLAMP pulse. If External
CLAMP is selected, the Offset DAC values only
change on the leading edge of CLAMP. If there is no
internal clamp signal, there will be up to a 100ms
delay between when the PGA gain or offset DAC
register is written to, and when the PGA or offset DAC
is actually updated.
1: XCLK
0 = XCLK
1 = XCLK
Pixel after HSYNC
DC restore and ABLC functions. 13-bits.
Set this register to the first stable black pixel following
the trailing edge of HSYNC
Width of DC restore clamp used in AC-coupled
configurations. Has no effect on ABLC. Minimum
value is 0x02 (a setting of 0x01 or 0x00 will not
generate a clamp pulse).
0: ABLC enabled (default)
1: ABLC disabled
Set to 0.
Number of black pixels averaged every line for ABLC
function
00: 16 pixels [default]
01: 32 pixels
10: 64 pixels
11: 128 pixels
ABLC Time constant (lines) = 2
000 = 32 lines
100 = 512 lines (default)
111 = 4096 lines
Set to 0.
OUT
OUT
OUT
OUT
IN
IN
pin enabled (default)
pin disabled (internally forced low)
= f
= f
enabled
is logic low
CRYSTAL
CRYSTAL
IN
DESCRIPTION
trailing edge to begin
/2
(default)
IN
.
(5+[6:4])
September 21, 2010
FN6148.5