74HCT125D,653 NXP Semiconductors, 74HCT125D,653 Datasheet - Page 11

• Manufacturer Part Number: 74HCT125D,653
• Description: IC BUFFER DVR TRI-ST QD 14SOICN
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT125D,653

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: 74HCT
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 6 mA
• Input Bias Current (max): 8 uA
• Low Level Output Current: 6 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 8 / 4
• Output Type: 3-State
• Propagation Delay Time: 12 ns
• Logical Function: Buffer/Line Driver
• Number Of Elements: 4
• Number Of Channels: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Quiescent Current: 8uA
• Technology: CMOS
• Pin Count: 14
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1509-2; 74HCT125D-T; 933757010653

Philips Semiconductors
Test circuit for 74HC
AC waveforms 74HC (continued)
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
L
T
=
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OFF-to-LOW
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
MGK562
OUTPUT
OUTPUT
OUTPUT
ENABLE
handbook, halfpage
GENERATOR
Fig.6 Propagation delays of 3-state outputs.
90%
PULSE
50%
t f
10%
t PLZ
enabled
outputs
t PHZ
Fig.5 Test circuit.
V I
10%
R T
90%
11
o
D.U.T
V CC
of
disabled
outputs
t r
V O
t PZL
t PZH
C L
FAMILY SPECIFICATIONS
MGK565
50%
50 pF
50%
outputs
enabled
V CC
GND