TLE 7269G Infineon Technologies, TLE 7269G Datasheet - Page 29

• Manufacturer Part Number: TLE 7269G
• Manufacturer: Infineon Technologies

Specifications of TLE 7269G

• Packages: PG-DSO-14
• Transmission Ratemax: 20.0 kbit/s
• Quiescent Current (max.): < 10 µA sleep mode
• Bus Wake-up Capability: Yes
• Additional Features: 2 x LIN trx, INH, EN, WK, Vio
• Wake-up Inputs: Bus wake-up + wake-up pin

7.3
To achieve the required timings for the dominant to recessive transition of the bus signal an additional external
termination resistor of 1 kΩ is mandatory. It is recommended to place this resistor at the master node. To avoid
reverse currents from the bus line into the battery supply line it is recommended to place a diode in series with the
external pull-up. For small systems (low bus capacitance) the EMC performance of the system is supported by an
additional capacitor of at least 1 nF at the master node (see
Termination resistor and the bus capacitance influence the performance of the LIN network. They depend on the
number of nodes inside the LIN network and on the parasitic cable capacitances of the LIN bus wiring.
7.4
A capacitor of 10 µF at the supply voltage input
reverse polarity diode this prevents the device from detecting a power down conditions in case of negative
transients on the supply line (see
The 100 nF capacitor close to the
to get the best EMC performance.
Data Sheet
Master Termination
External Capacitors
Figure 17
V
S
pin and a 33 nF capacitor close to the
and
Figure
V
S
buffers the input voltage. In combination with the required
29
18).
Figure 17
and
V
Figure
IO
pin of the TLE7269G are required
18).The values for the Master
Application Information
Rev. 1.2, 2007-11-13
TLE7269G