IW4051BD Integral Corp., IW4051BD Datasheet
IW4051BD
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IW4051BD Summary of contents
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... H = high level L = low level X = don’t care TECHNICAL DATA IW4051B N SUFFIX PLASTIC SUFFIX SOIC 16 1 ORDERING INFORMATION IW4051BN Plastic DIP IW4051BD SOIC IZ4051B chip T = -55° to 125° C for all packages A PIN ASSIGNMENT FUNCTION TABLE Control Inputs ON Enable Select Channels C B ...
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MAXIMUM RATINGS * Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Input Current, per Pin IN P Power Dissipation in Still Air D P Power Dissipation per Output Transistor ...
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DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage, Channel-Select or Enable Inputs V Maximum Low -Level IL Input Voltage, Channel-Select or Enable Inputs I Maximum Input IN Leakage Current, Channel-Select or Enable Inputs I Maximum Quiescent CC ...
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AC ELECTRICAL CHARACTERISTICS Symbol Parameter t t Maximum Propagation Delay , Analog Input to PHL PLH ( ) Analog Output (Figure 1) R =200kΩ, V =GND Maximum Propagation Delay , Channel-Select PHL PLH 1( 1) Input ...
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ADDITIONAL APPLICATION CHARACTERISTICS Symbol Parameter B Maximum On Channel R L Bandwidth or 20 log(V Minimum Frequency OUT/IN Response (-3db) f (-40db Feedthrough L 20 log(V Frequency (All Channels OFF) OUT/IN f (-40db) ...
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INPUT ANALOG OUT ANALOG OUT EXPANDED LOGIC DIAGRAM Ucc Logic Level Conversion ENABLE 8 7 GND 50% t PLH 90% 50% ...
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Location of marking (mm): left lower corner x=1.369, y=0.223; right higher corner x=1.495, y=0.259. Chip thickness: 0.46±0.02mm PAD LOCATION Pad No Pin ...