S25FL032P Meet Spansion Inc., S25FL032P Datasheet
S25FL032P
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S25FL032P Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL032P_00 Notice On Data Sheet Designations Revision 02 Issue Date February 12, 2009 S25FL032P Cover Sheet for definitions. ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL032P S25FL032P_00_02 February 12, 2009 ...
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... Publication Number S25FL032P_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications ...
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... This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL032P device also offers a One-Time Programmable area (OTP 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions ...
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... OTP Program (OTPP 9.23 Read OTP Data Bytes (OTPR 10. OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 Programming OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 Reading OTP Data 10.3 Locking OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 February 12, 2009 S25FL032P_00_02 S25FL032P 5 ...
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... SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width 19.3 USON 8-contact ( mm) No-Lead Package 19.4 WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL032P S25FL032P_00_02 February 12, 2009 ...
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... AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18.2 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 18.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = February 12, 2009 S25FL032P_00_02 S25FL032P 7 ...
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... Table 7.1 Configuration Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 7.2 TBPROT = 0 (Starts Protection from TOP of Array .17 Table 7.3 TBPROT=1 (Starts Protection from BOTTOM of Array .17 Table 8.1 S25FL032P Sector Address Table TBPARM .19 Table 8.2 S25FL032P Sector Address Table TBPARM .20 Table 9.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh .31 Table 9.3 Product Group CFI Query Identification String ...
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... Block Diagram SRAM Logic 2. Connection Diagrams Note DNC = Do Not Connect (Reserved for future use) February 12, 2009 S25FL032P_00_02 Array - Figure 2.1 16-pin Plastic Small Outline Package (SO HOLD#/IO3 VCC ...
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... Functions as an output pin in Quad I/O mode. Supply Voltage Ground S25FL032P 8 VCC 7 HOLD#/IO3 SCK 6 5 SI/IO0 VCC HOLD#/IO3 SCK SI/IO0 VCC HOLD#/IO3 SCK SI/IO0 S25FL032P_00_02 February 12, 2009 ...
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... Logic Symbol February 12, 2009 S25FL032P_00_02 SI/IO0 SCK CS# W#/ACC/IO2 HOLD#/IO3 GND S25FL032P SO/IO1 11 ...
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... Device Family S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL032P Valid Combinations Table S25FL032P Valid Combinations Package & Speed Option Temperature MFI 0X NFI S25FL032P Packing Type (Note 1) 0 ...
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... The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL Mode 0 0 Mode 3 1 February 12, 2009 S25FL032P_00_02 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK ...
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... Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL032P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure. ...
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... When TBPROT is set to a ‘1’, then the block protection is defined to start from the bottom of the array. Note that once this bit is set to a '1', it cannot be changed back to '0'. Note: In case BPNV=1 (Volatile), the BP2-0 bits will always be considered as non-volatile. February 12, 2009 S25FL032P_00_02 Table 9.8, S25FL032P Status Register on page S25FL032P 36): 15 ...
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... Not Used 1 = Bottom Array (low address Top Array (high address) (Default) Not Used 1 = Volatile 0 = Non-volatile (Default Top Array (high address Bottom Array (low address) (Default Quad I Dual or Serial I/O (Default Enabled 0 = Disabled (Default) Table 7.2 and Table 7.3 shows the sizes S25FL032P_00_02 February 12, 2009 ...
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... Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. Note: The HOLD Mode feature is disabled during Quad I/O Mode. February 12, 2009 S25FL032P_00_02 Table 7.2 TBPROT = 0 (Starts Protection from TOP of Array) ...
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... Figure 7.1 Hold Mode Operation Hold Condition (standard use) (non-standard use) S25FL032P Hold Condition on this pin, the S25FL032P_00_02 February 12, 2009 ...
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... Sector SA0 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA1 is split up into sub-sectors SS16 - SS31(light gray shading) February 12, 2009 S25FL032P_00_02 Table 8.1 S25FL032P Sector Address Table TBPARM=0 Address range Sector End address Start address ...
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... Sector SA62 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA63 is split up into sub-sectors SS16 - SS31 (light gray shading Table 8.2 S25FL032P Sector Address Table TBPARM=1 Address Range Sector End Address Start Address End Address ...
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... The device ignores any attempt to access the memory array during a Write Registers, program, or erase operation, and continues the operation uninterrupted. The instruction set is listed in February 12, 2009 S25FL032P_00_02 Table 9.1 lists the complete set of commands. ...
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... S25FL032P_00_02 February 12, 2009 ...
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... READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS# 0 Mode 3 SCK Mode 0 SI Hi-Z SO February 12, 2009 S25FL032P_00_02 detail the READ command sequence. The first address byte specified Figure 9.1 Read Data Bytes (READ) Command Sequence ...
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... Bit Address S25FL032P ) presented at the SCK SCK and Table 9.1 on page 22. The first address Dummy Byte MSB MSB DATA OUT 1 S25FL032P_00_02 February 12, 2009 DATA OUT 2 ...
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... Dual Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS SCK SI/IO0 Hi-Z SO/IO1 February 12, 2009 S25FL032P_00_02 the falling edge of SCK. SCK Figure 9.3 Figure 9.3 Dual Output Read Instruction Sequence 2 5 ...
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... SCK and Table 9.1 on page 22. The first SI Switches from Input to Output DATA DATA DATA DATA OUT 1 OUT 2 OUT 3 OUT 4 *MSB S25FL032P_00_02 February 12, 2009 ...
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... Figure 9.5 DUAL I/O High Performance Read Instruction Sequence CS SCK SI/IO0 Hi-Z SO/IO1 February 12, 2009 S25FL032P_00_02 Figure 9.6, thus eliminating eight cycles for the instruction sequence ...
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... Bit Address Mode Bits S25FL032P IO0 & IO1 Switches from Input to Output *MSB Byte 2 Byte 1 S25FL032P_00_02 February 12, 2009 ...
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... CS# 0 SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 February 12, 2009 S25FL032P_00_02 Figure 9.8, thus eliminating eight cycles for the instruction sequence. Figure 9.7 QUAD I/O High Performance Instruction Sequence 1 2 ...
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... Command Manufacturer Identification MSB S25FL032P IO’s Switches from Input to Output Byte 1 Byte 2 *MSB Table 9.3. 22 Device Identification S25FL032P_00_02 February 12, 2009 ...
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... February 12, 2009 S25FL032P_00_02 Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh): Manuf. ID Byte 0 01h Table 9.3 Product Group CFI Query Identification String Data 51h 52h Query Unique ASCII string “ ...
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... Erase Block Region 2 Information (refer to CFI publication 100) 00h 01h 00h 00h Erase Block Region 3 Information (refer to CFI publication 100) 00h 00h 00h 00h Erase Block Region 4 Information (refer to CFI publication 100) 00h 00h S25FL032P Description N S25FL032P_00_02 February 12, 2009 ...
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... CFI data related to V and time-outs may differ from actual V CC tables to obtain the V range for particular part numbers. Please consult the CC specifications. February 12, 2009 S25FL032P_00_02 Data 50h 52h Query-unique ASCII string “PRI” ...
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... Read-ID (READ_ID) The READ_ID instruction provides the S25FL032P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “ ...
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... Quad Page Program (QPP) completion Parameter Sector Erase (P4E, P8E) completion Sector Erase (SE) command completion Bulk Erase (BE) command completion OTP Program (OTPP) completion February 12, 2009 S25FL032P_00_02 Figure 9.11) sets the Write Enable Latch (WEL) bit which Figure 9 ...
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... BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page Program (PP Table 9.8 S25FL032P Status Register Bit Function 1 = Protects when W#/ACC is low Status Register Write Disable protection, even when W#/ACC is low ...
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... The Configuration Register originally shows 00h when the device is first shipped from the factory to the customer. Figure 9.14 Read Configuration Register (RCR) Instruction Sequence CS SCK High Impedance SO February 12, 2009 S25FL032P_00_02 ...
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... If not, the Write Registers (WRR) instruction is not MSB High Impedance S25FL032P Table 9.9 shows that W#/ACC must be Figure 9.15 S25FL032P_00_02 February 12, 2009 ...
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... If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be used. The Status and Configuration registers originally default to 00h, when the device is first shipped from the factory to the customer. February 12, 2009 S25FL032P_00_02 ...
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... MSB S25FL032P and Table 9.1 on page 22. . The Status Register may Data Byte MSB Data Byte 256 MSB S25FL032P_00_02 February 12, 2009 ...
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... Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown below. CS# SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 CS# SCK SI/IO0 4 5 SO/IO1 W#/ACC/IO2 6 HOLD#/IO3 February 12, 2009 S25FL032P_00_02 Figure 9.18 QUAD Page Program Instruction Sequence Bit Instruction ...
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... Table 5.1 on page 12 valid address for the P4E or P8E command. 22 Instruction 24 Bit Address 20h or 40h MSB S25FL032P S25FL032P_00_02 February 12, 2009 ...
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... The device only executes a SE command if all Block Protect bits (BP2:BP0) are 0 (see on page 17). Otherwise, the device ignores the command. CS# Mode 3 SCK Mode 0 SI Hi-Z SO February 12, 2009 S25FL032P_00_02 Table 7.2 on page 17 valid address for the SE command. CS# must be Figure 9.20 Sector Erase (SE) Command Sequence ...
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... Otherwise, the device ignores the command. CS# SCK Figure 9.21 Bulk Erase (BE) Command Sequence Mode Mode 0 Command Hi-Z S25FL032P Figure 9.21 and Table 9.1 . The Status Register may BE Table 7 S25FL032P_00_02 February 12, 2009 ...
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... The device rejects any DP command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS# Mode 3 SCK Mode 0 SI Hi-Z SO February 12, 2009 S25FL032P_00_02 DP, (see Table 16.1 on page 55). Section 9.20 and 9.20.1). ...
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... after the 8-bit RES command byte. The device transitions RES(max) (see RES Mode 3 Mode 0 Command Hi-Z Deep Power-down Mode S25FL032P Figure 9.23 and Table 9.1 on page Figure 18.1). In the standby mode, the device RES Standby Mode S25FL032P_00_02 February 12, 2009 22. ...
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... WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be unchanged after this command is executed. This command also resets the State machine and loads latches SCK SI February 12, 2009 S25FL032P_00_02 for the command sequence and signature value. The Electronic 2 ...
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... Data Byte MSB “OTP Regions” for details DATA OUT 1 DATA OUT MSB MSB S25FL032P_00_02 February 12, 2009 ...
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... OTP Read operations outside the valid OTP address range will yield indeterminate data. 10.3 Locking OTP Regions In order to permanently lock the ESN and OTP regions, individual bits at the specified addresses can be set to lock specific regions of OTP memory, as highlighted in Figures February 12, 2009 S25FL032P_00_02 S25FL032P Section 10 ...
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... N2) 8 bytes (ES N1) Reserved Bit 1 Bit 0 S25FL032P Address B it Locks R egion… 0 OTP1 0x112h 1 OTP2 2 OTP3 3 OTP4 4 OTP5 5 OTP6 6 OTP7 7 OTP8 0 OTP9 0x113h 1 OTP10 2 OTP11 3 OTP12 4 OTP13 5 OTP14 6 OTP15 7 OTP16 0 ESN1 0x100h eserved S25FL032P_00_02 February 12, 2009 ...
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... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x214h Note 1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored. February 12, 2009 S25FL032P_00_02 Figure 10.2 OTP Memory Map - Part EGION 10 bytes (OTP31) ...
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... CC Figure 11.1 Power-Up Timing Diagram V cc (max) cc (min Figure 11.2 Power-down and Voltage Drop S25FL032P reaches the allowable values as follows CC rises to the threshold at power-down, all CC Full Device Access Time S25FL032P_00_02 February 12, 2009 min., feed. ...
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... The W#/ACC pin is disabled during Quad I/O mode. Symbol VHH t WC February 12, 2009 S25FL032P_00_02 Table 11.1 Power-Up / Power-Down Voltage and Timing Parameter (minimum operation voltage) (Cut off where re-initialization is needed) (Low voltage for initialization to occur at read/standby) (Low voltage for initialization to occur at embedded) (min ...
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... Figure 14.2 Maximum Positive Overshoot Waveform +2. +0.5V 2. Table 15.1 Operating Ranges Description ) Industrial A Voltage Range S25FL032P Rating -65°C to +150°C -0. +0.5V CC 200 mA to -2.0V for periods Rating –40°C to +85°C 2.7V to 3.6V S25FL032P_00_02 February 12, 2009 ...
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... I Standby Current SB1 I Deep Power-down Current PD *Typical values are 25°C and V AI Note Typical values are 25°C and 3.0V. A February 12, 2009 S25FL032P_00_02 Table 16.1 DC Characteristics (CMOS Compatible) Parameter Test Conditions V = 2. 1.6 mA ...
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... Min. Typ Max (Notes) (Notes) (Notes 104 (serial (dual/quad) 12.0 6.0 4.6 12.0 6.0 4.6 0.1 0 (Serial)Δ 9.5 (Dual/Quad)Δ 0 6.5 (Serial)∞ 8 (Dual/Quad)∞ 7 (Dual/Quad)Ω S25FL032P_00_02 February 12, 2009 Unit MHz ns ns V/ns V/ ...
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... Regulated Vcc range (3.0 – 3.6V) & 18.1 Capacitance Symbol Input Capacitance C IN (applies to SCK, PO7-PO0, SI, CS#) Output Capacitance C OUT (applies to PO7-PO0, SO) CS# t SCK SI Hi-Z SO February 12, 2009 S25FL032P_00_02 Figure 18.1 AC Characteristics (Sheet Parameter (Notes) (4) (4) (1)(2) (1)(2)(3) (1)(2) (1)(2) (1)(2) = 2.7V; 100,000 cycles. CC Parameter Test Conditions V ...
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... SCK SI Hi Figure 18.3 SPI Mode 0 (0,0) Output Timing Figure 18.4 HOLD# Timing t t HLCH CHHL t CHHH WPS S25FL032P DIS LSB OUT t HHCH WPH S25FL032P_00_02 February 12, 2009 ...
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... BSC e .050 BSC 1.27 BSC L 0.020 0.030 0.508 L1 .055 REF 1.40 REF L2 .010 BSC 0.25 BSC N 8 0˚ 8˚ 0˚ 5˚ 15˚ 5˚ 0˚ February 12, 2009 S25FL032P_00_02 0. SEE DETAIL E 0.10 C 0.10 C ...
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... LOWER RADIUS OF THE LEAD FOOT. 0.75 9. THIS CHAMFER FEATURE IS OPTIONAL NOT PRESENT, 8˚ THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 15˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED 0˚ FROM THE SEATING PLANE. S25FL032P 3601 \ 16-038.03 \ 8.31.6 S25FL032P_00_02 February 12, 2009 ...
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... E 6.00 BSC A 0.45 0.50 A1 0.00 0.02 K 0.20 MIN. 0 --- February 12, 2009 S25FL032P_00_02 NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTE 2. ALL DIMENSIONS ARE IN MILLIMETERS DEGREES THE TOTAL NUMBER OF TERMINALS DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS 5 MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. ...
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... PIN # TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT S25FL032P (ND- 0. SEE DETAIL "A" BOTTOM VIEW 3408\ 16-038.28a S25FL032P_00_02 February 12, 2009 ...
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... DC Characteristics Modified Test Conditions for I Changed maximum specifications for t Changed typical time for t AC Characteristics Added note for max values assume 100k cycles. Changed Clock High/Low time. February 12, 2009 S25FL032P_00_02 Description . PU and I CC1 and I ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion Logo, MirrorBit S25FL032P ® ™ ™ , MirrorBit Eclipse , ORNAND , S25FL032P_00_02 February 12, 2009 ...