M25P80-VMP6TP Numonyx, B.V., M25P80-VMP6TP Datasheet - Page 13

• Manufacturer Part Number: M25P80-VMP6TP
• Description: 8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
• Manufacturer: Numonyx, B.V.

M25P80
4.4
4.5
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S) is High, the device is disabled, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down mode (DP) instruction) is executed. The device consumption drops further to
I
Deep Power-down mode and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P80 boasts the following data protection mechanisms:
●
●
●
●
●
●
CC2
. The device remains in this mode until another specific instruction (the Release from
Section 6.4: Read Status Register
Power-On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
(RDSR).
PUW
) can provide protection against
Operating features
CC1
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