A43L0632G-7UF AMIC Technology, Corp., A43L0632G-7UF Datasheet - Page 12

• Manufacturer Part Number: A43L0632G-7UF
• Description: 512K x 32-Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Device Operations
Clock (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock for proper functionality and ICC specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “t
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.
Bank Select (BA)
This SDRAM is organized as 2 independent banks of
524,288 words X 32 bits memory arrays. The BA inputs is
latched at the time of assertion of RAS and
the bank to be used for the operation. The bank select BA is
latched at bank activate, read, write mode register set and
precharge operations.
Address Input (A0 ~ A10/AP)
The 19 address bits required to decode the 524,288 word
locations are multiplexed into 11 address input pins
(A0~A10/AP). The 11 bit row address is latched along with
address is latched along with
or write command.
NOP and Device Deselect
When RAS ,
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS
command decoder so that RAS ,
the address inputs are ignored.
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
PRELIMINARY
RAS , BA during bank activate command. The 8 bit column
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
SS
+ 1
CLOCK
CAS
(August, 2005, Version 0.0)
” before the high going edge of the
and
WE
CAS
CAS
are high, the SDRAM
,
WE
high disables the
and
, BA during read
CAS
WE
, and all
to select
11
2. After VDD reaches the desired voltage, a minimum pause
3. All banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
5. Perform a MODE REGISTER SET cycle to program the
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SDRAM useful for variety of
different applications. The default value of the mode register
is not defined, therefore the mode register must be written
after power up to operate the SDRAM. The mode register is
written by asserting low on CS , RAS ,
SDRAM should be in active mode with CKE already high
prior to writing the mode register). The state of address pins
A0~A10/AP,
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A10/AP, BA are used for vendor specific options or
test mode. And the write burst length is programmed using
A7~A9, A10/AP, BA must be set to low for normal SDRAM
operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies. BA have to be set to
“0” to enter the Mode Register.
Bank Activate
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
t
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
t
the result to the next higher integer. The SDRAM has 2
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of both banks simultaneously. Also the noise
generated during sensing of each bank of SDRAM is high
CS , RAS , CAS ,
RCD
RCD
The clock signal must also be asserted at the same time.
of 200 microseconds is required with inputs in NOP
condition.
the internal circuitry.
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
(min) from the time of bank activation. t
(min) with cycle time of the clock and then rounding off
BA
WE
in
going low is the data written in the
AMIC Technology, Corp.
the
same
A43L0632
CAS
RCD
cycle
(min) is an
,
WE
CS
(The
with
as