A43L0632G-7UF AMIC Technology, Corp., A43L0632G-7UF Datasheet - Page 14

• Manufacturer Part Number: A43L0632G-7UF
• Description: 512K x 32-Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

required can be calculated by dividing “t
time and then rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. All banks will be in the
idle state at the end of auto refresh operation. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 15.6us or a burst of 4096
auto refresh cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
PRELIMINARY
(August, 2005, Version 0.0)
RC
” with clock cycle
13
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
state to begin normal operation. Upon exiting the self refresh
mode, AUTO REFRESH commands must be issued every
15.6 μ s or less as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
WE . Once the self refresh mode is entered, only CKE state
CS
,
RAS
AMIC Technology, Corp.
RC
” before the SDRAM reaches idle
,
CAS
and CKE with high on
A43L0632