IXF1110 Intel, IXF1110 Datasheet
IXF1110
Related parts for IXF1110
IXF1110 Summary of contents
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... Applications ® In general, the Intel IXF11101000 Mbps Ethernet Media Access Controller (called hereafter the IXF1110 MAC) is appropriate for high-end switching applications where MAC and SerDes functions are not integrated into the system ASIC. High-End Optical Ethernet Switches Multi-Service Optical Ethernet Switches ...
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... The Intel IXF1110 MAC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ...
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... Data Path ...............................................................................................................59 5.2.1.1 Control Words ........................................................................................ 60 5.2.1.2 EOP Abort.............................................................................................. 62 5.2.1.3 DIP4 ....................................................................................................... 63 5.2.2 Start-Up Parameters .............................................................................................. 64 5.2.2.1 CALENDAR_LEN .................................................................................. 64 5.2.2.2 CALENDAR_M ...................................................................................... 65 5.2.2.3 DIP2_Thr................................................................................................ 65 5.2.2.4 Loss_Of_Sync........................................................................................ 65 5.2.2.5 DATA_MAX_T ....................................................................................... 65 5.2.2.6 REP_T ................................................................................................... 65 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 3 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 5.2.2.7 DIP4_UnLock......................................................................................... 65 5.2.2.8 DIP4_Lock ............................................................................................. 65 5.2.2.9 MaxBurst1.............................................................................................. 66 5.2.2.10 MaxBurst2.............................................................................................. 66 5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew) ................... 66 5.2.3.1 Training at Start-up ................................................................................ 66 5.2.3.2 Periodic Training .................................................................................... 66 5.2.3.3 Training in a Practical Implementation................................................... 67 5.2.4 FIFO Status Channel ............................................................................................. 67 5.2.5 DC Parameters ...................................................................................................... 71 5.3 SerDes Interface ................................................................................................................ 71 5.3.1 Introduction ............................................................................................................ 71 5.3.2 Features................................................................................................................. 71 5.3.3 Functional Description ........................................................................................... 72 5 ...
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... SerDes Power-Down Capabilities..................................................................................... 102 6.5.1 Placing the SerDes Port in Power-Down Mode ................................................... 102 6.5.2 Bringing the SerDes Port Out of Power-Down Mode...........................................103 6.6 IXF1110 MAC Unused Ports ............................................................................................ 103 6.7 Optical Module Connections to the IXF1110 MAC ........................................................... 103 6.7.1 SFP-to-IXF1110 Connection................................................................................ 103 7.0 Electrical Specifications ........................................................................................................... 106 7.1 DC Specifications .............................................................................................................108 7.2 Undershoot/Overshoot Specifications .............................................................................. 109 7 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 8.0 Register Definitions................................................................................................................... 123 8.1 Introduction ....................................................................................................................... 123 8.2 Document Structure.......................................................................................................... 123 8.3 Graphical Representation ................................................................................................. 123 8.4 Per Port Registers ............................................................................................................ 125 8.5 Memory Map..................................................................................................................... 125 8.5.1 MAC Control Registers ........................................................................................ 133 8.5.2 MAC RX Statistics Register Overview ................................................................. 141 8.5.3 MAC TX Statistics Register Overview ................................................................. 145 8 ...
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... IXF1110-to-SFP Connections..................................................................................................... 74 23 LED Signal Descriptions ............................................................................................................. 84 24 Mode 0 Clock Cycle to Data Bit Relationship ............................................................................. 85 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 7 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 25 Mode 1 Clock Cycle to Data Bit Relationship ............................................................................. 86 26 LED Data Decodes ..................................................................................................................... 87 27 LED Behavior............................................................................................................................. 88 28 CPU Interface Signals ................................................................................................................ 89 29 Recommended JTAG Termination ............................................................................................. 92 30 Supported Boundary Scan Instructions ...................................................................................... 93 31 Power Sequencing ..................................................................................................................... 97 32 Analog Power Balls .................................................................................................................... 97 33 SFP-to-IXF1110 Connection ...
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... C Control Ports 0-9 ($ 0x79B) ...............................................................................................177 2 111 I C Data Ports 0-9 ($ 0x79C).................................................................................................... 178 112 Product Ordering Information ................................................................................................... 183 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 9 ...
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... Removed Short Runts Threshold Register ($ Port_Index 0x14) and changed to Reserved in 125 “Table 51 “MAC Control Register Page # 1 Changed product ordering number to reflect B2 [HFIXF1110CC.B2: 860817]. Modified Table 11 “Power Supply Signal Descriptions” [changed AVDD to AVDD1P8_1/2 and 41 AVDD2 to AVDD2P5_1/2]. 42 Added note under Section 5.1.2.1, “Padding of Undersized Frames on Transmit”. ...
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... B2]. Page # NA Deleted old Table 19: 1x9-to-IXF1110 Connection 136 Modified text under Section 6.5, “SerDes Power-Down Capabilities (IXF1110 Only)”. NA Changed Table 98: TX FIFO Port Reset Register (Addr: 0x620) to Reserved. Page # Added product ordering and operating temperature range information, and changed SFF-8053, 1 Revision 5 ...
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... Revision Number: 005 (Sheet Revision Date: November 24, 2003 Description ® IXF1110 SerDes Driver TX Power Levels”. ® IXF1110 2.5 V LVTTL and CMOS I/O Electrical Characteristics”. ® IXF1110 CPU Timing Parameters”. ® IXF1110 Transmitter Characteristics”. ® IXF1110 Receiver Characteristics” (added Common Mode Voltage Spec). ...
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... Added Table 107 “SerDes Tx Driver Power Level Ports 7-9 Register (Addr: 0x785)”. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Revision Number: 005 (Sheet Revision Date: November 24, 2003 Description Order Number: 250210, Revision: 009 07-Oct-2005 13 ...
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... IXF1110 MAC block diagram system architecture. • Section 3.0, “Ball Assignments and Ball List Tables” on page 18 IXF1110 MAC ball grid diagram with two ball list tables (by pin number and signal name) • Section 4.0, “Ball Assignments and Signal Descriptions” on page 19 Signal naming methodology and signal descriptions. ...
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... Related Documents ® Intel IXF1110 MAC Specification Update ® Intel IXF1010 and IXF1110 10-Port Gigabit Ethernet Media Access Controllers Design and Layout Guide ® Intel IXF1110 Demo Board Development Kit Manual ® Intel SPI4 Phase 2 Performance in Gigabit Ethernet Media Access Controllers Application ...
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... General Description ® The Intel IXF1110 MAC is a 10-port 1000 Mbps Ethernet Media Access Controller (MAC). The 10 Gigabit interface to the network processor is supported through a System Packet Interface Level 4 Phase 2 (SPI4-2), and the media interface is an integrated Serializer/Deserializer (SerDes). Figure 1 illustrates the IXF1110 MAC block system block diagram ...
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... Figure 2. IXF1110 MAC System Block Diagram LED Serial-to-Parallel Converter Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Forwarding Engine Network Processor SPI4-2 IXF1110 LED Serial Interface SerDes/Optical Module Interface § ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 3.0 Ball Assignments and Ball List Tables Figure 3 illustrates the IXF1110 MAC 552-Ball CBGA assignments. ball list tables in alphanumeric order by signal name and ball location under Tables” on page 32. Figure 3. 552-Ball CBGA Assignments (Top View) ...
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... Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory location in Hex. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 2 2 C_DATA_0, I C_DATA_1, etc. 07-Oct-2005 19 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 4.2 Interface Signal Groups This section describes the IXF1110 MAC signals in groups according to the associated interface or function. Figure 4 and Balls/Reserved” describe the signals used by the IXF1110 MAC. Figure 4. Interface Diagram SPI4-2 ...
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... TDAT2_P, TDAT2_N TDAT1_P, TDAT1_N TDAT0_P, TDAT0_N TDCLK_P TDCLK_N TCTL_P TCTL_N TSCLK TSTAT1 TSTAT0 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard G11 H11 K10 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 1. SPI4-2 Interface Signal Descriptions (Sheet Signal Name RDAT15_P, RDAT15_N RDAT14_P, RDAT14_N RDAT13_P, RDAT13_N RDAT12_P, RDAT12_N RDAT11_P, RDAT11_N RDAT10_P, RDAT10_N RDAT9_P, RDAT9_N RDAT8_P, RDAT8_N RDAT7_P, RDAT7_N RDAT6_P, RDAT6_N RDAT5_P, RDAT5_N ...
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... RX_P_5, RX_N_5 RX_P_6, RX_N_6 RX_P_7, RX_N_7 RX_P_8, RX_N_8 RX_P_9, RX_N_9 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard V20 V21 Y19 Y20 V22 W22 Y23 ...
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... UPX_DATA10 UPX_DATA9 UPX_DATA8 UPX_DATA7 UPX_DATA6 UPX_DATA5 UPX_DATA4 UPX_DATA3 UPX_DATA2 UPX_DATA1 UPX_DATA0 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 24 Ball Designator Type Standard 2 Input CMOS E3 ...
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... Pause Control Interface Signal Descriptions Signal Name TXPAUSEFR TXPAUSEADD3 TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard 2.5 V A18 Input CMOS 2.5 V H14 Input CMOS Open 2 ...
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... TX_DISABLE_2 TX_DISABLE_3 TX_DISABLE_4 TX_DISABLE_5 TX_DISABLE_6 TX_DISABLE_7 TX_DISABLE_8 TX_DISABLE_9 TX_FAULT_INT 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 26 Ball Designator Type Standard M24 V23 Y17 R15 W14 2.5 V Input W11 ...
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... Table 6. LED Interface Signal Descriptions Signal Name LED_CLK LED_DATA LED_LATCH Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type Standard Open 2.5 V B14 Drain CMOS Output* Open 2.5 V ...
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... JTAG Interface Signal Descriptions Signal Name TCK TMS TDI TRST_L TDO Table 8. System Interface Signal Descriptions Signal Name CLK125 CLK50 SYS_RES_L 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 28 Ball Designator Type Standard 3.3 V AA24 Input LVTTL 3.3 V T16 Input LVTTL 3.3 V AC18 Input LVTTL 3 ...
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... Power Supply Signal Descriptions (Sheet Signal Name AVDD1P8_1 AVDD1P8_2 AVDD2P5_1 AVDD2P5_2 VDD VDD2 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type D1 E24 – P7 P18 V6 V11 – V14 V18 Y1 – ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 9. Power Supply Signal Descriptions (Sheet Signal Name GND 07-Oct-2005 ® Intel IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 30 Ball Designator Type B6 B10 B15 B19 D12, D13 ...
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... Table 10. Unused Balls/Reserved Signal Name NC No Ball No Pad Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type A5 A6 C10 C15 G7 G8 H22 J22 K7 L21 L23 M1 M7 ...
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... AVDD2P5_2 AVDD2P5_2 AVDD2P5_2 CLK125 CLK50 GND GND GND GND GND GND GND GND GND GND GND 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 32 Signal Ball Ball GND D21 D1 GND D22 E24 GND D24 P7 GND E1 P18 GND F2 V6 ...
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... GND GND GND GND GND GND GND GND GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal Ball P15 GND W3 P21 GND W5 P23 GND W6 P24 GND ...
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... 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 34 Ball Signal Ball M7 NC AB22 N1 NC AD4 N5 NC AD5 N7 NC AD6 N20 NC AD7 P4 NC AD8 P5 NC AD17 P6 NC ...
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... TDAT0_N TDAT0_P TDAT1_N TDAT1_P TDAT2_P TDAT3_N TDAT3_P TDAT4_N TDAT4_P TDAT5_N Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal Ball Y9 TDAT5_P G5 AC3 TDAT6_N L7 T2 TDAT6_P L8 P2 TDAT7_N C6 ...
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... UPX_DATA11 UPX_DATA12 UPX_DATA13 UPX_DATA14 UPX_DATA15 UPX_DATA16 UPX_DATA17 UPX_DATA18 UPX_DATA19 UPX_DATA20 UPX_DATA21 UPX_DATA22 UPX_DATA23 UPX_DATA24 UPX_DATA25 UPX_DATA26 UPX_DATA27 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 36 Ball Signal Ball F3 UPX_DATA28 B18 H1 UPX_DATA29 A21 E3 UPX_DATA30 B22 E2 UPX_DATA31 C23 G1 UPX_RD_L H14 ...
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... VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball N9 N12 N13 N16 N19 N23 T12 T13 U2 U6 U19 U23 W8 ...
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... A24 No Ball B1 No Ball B2 No Ball B3 UPX_DATA0 B4 VDD2 B5 TDAT2_P B6 GND B7 TDAT9_P B8 VDD2 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 38 Ball Signal B9 UPX_DATA2 B10 GND B11 TX_FAULT_INT B12 VDD2 B13 VDD2 B14 RX_LOS_INT B15 GND B16 UPX_DATA22 B17 ...
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... VDD2 F13 VDD2 F14 UPX_DATA18 F15 GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal F16 RDAT14_P F17 VDD2 F18 RDAT2_P F19 GND F20 UPX_CS_L F21 ...
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... L4 TX_DISABLE_9 L5 TDAT8_P L6 GND L7 TDAT6_N L8 TDAT6_P L9 VDD L10 GND L11 VDD L12 GND 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 40 Ball Signal L13 GND L14 VDD L15 GND L16 VDD L17 RDAT5_P L18 RDAT5_N 2 L19 I C_CLK L20 RSTAT0 ...
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... TX_P_9 GND T8 GND T9 GND Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Signal T10 GND T11 VDD T12 VDD2 T13 VDD2 T14 VDD T15 GND T16 ...
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... TX_P_3 Y24 TDO AA1 GND AA2 VDD2 AA3 GND AA4 GND AA5 CLK125 AA6 VDD 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 42 Ball Signal AA7 GND AA8 GND AA9 TX_DISABLE_7 AA10 VDD AA11 NC AA12 GND AA13 GND ...
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... RX_P_7 AD17 NC AD18 RX_LOS_2 AD19 NC AD20 NC AD21 GND AD22 No Ball AD23 No Ball AD24 No Ball Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 07-Oct-2005 43 ...
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... IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 5.0 Functional Descriptions 5.1 Media Access Controller 5.1.1 General Description The IXF1110 MAC main functional block consists of a 1000 Mbps Ethernet Media Access Controller (MAC), supporting the following features: • 1000 Mbps full-duplex operation • Independent enable/disable of any port • ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 74, “RX Packet Filter Control ($ 139, are sent across the SPI4-2 interface as an EOP abort frame. Table 74, “RX Packet Filter Control ($ are actually dropped by the RX FIFO and counted in the RX ...
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... CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 46 “RX Packet Filter Control ($ Port_Index + 0x19)” “RX Packet Filter Control ($ Port_Index + 0x19)” ...
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... RX FIFO thresholds called watermarks. The RX FIFO level rises and falls as packets are received and processed. When the RX FIFO reaches a watermark (either exceeding a High or dropping below a Low after exceeding a High), the IXF1110 MAC control sublayer signals an internal state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE frames (also called control frames) to initiate the following: • ...
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... Figure 6. Ethernet Frame Format Number of bytes Preamble 64 yte Minimum / 1518 bytes Maximum Note: 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 48 TX FIFO Data Flow Data Flow RX FIFO RX FIFO High 802.3 Flow control 802 ...
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... Preamble ® Note: In the Intel IXF1110 architecture, the TX block of the MAC sets this as the pause multicast address. The RX interface of the MAC will process this as the pause multicast or the MAC address. An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following: • ...
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... Destinations Address matching the address programmed in the Low ($ Port_Index + 0x00)" the PAUSE frame is valid, the transmit side of the IXF1110 MAC pauses for the required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31. 3. PAUSE does not begin until completion of the frame currently being transmitted. ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller TX Pause Control Interface Operation Transmits a PAUSE frame on port 5 with pause_time equal to the value programmed in the port 5 “FC TX Timer Value ($ Port_Index + 0x07)" ...
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... Note: Packet IPG must contain a minimum of three consecutive /I1/ or /I2/ ordered sets per IEEE 802.3 for correct operation. Note: The IXF1110 treats the K28.1 code word as an unknown control word; therefore, it should not be used. 5.1.5 Auto-Negotiation Auto-negotiation is carried out by an internal state machine within the MAC in the IXF1110. The IXF1110 is fully IEEE 802 ...
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... Jumbo Packet Support The IXF1110 MAC supportss the concept of jumbo frames. The jumbo frame length is dependent on the application, and the IXF1110 MAC design has been optimized for 9.6 KB jumbo frame length. Lengths larger than this can be programmed, but will limit system performance. ...
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... RMON Statistics The IXF1110 MAC supplies RMON statistics via the CPU interface. These statistics are available in the form of counter values that can be accessed at specific addresses in the IXF1110 MAC memory map. Once read, these counters automatically reset and begin counting from zero. A separate set of RMON statistics is available for each MAC device in the IXF1110 MAC ...
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... The RX/TX FIFO Number of Frames Removed Register in the IXF1110 MAC supports this and will increment when either FIFO has over flowed. If any IXF1110 MAC programmable packet filtering is enabled, the RX/TX Number of Frames Removed Register increments with every frame removed in addition to the existing frames counted due to FIFO overflow ...
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... The RX/TX FIFO Number of Frames Removed Register in the IXF1110 MAC supports this and will increment when either FIFO has over flowed. If any IXF1110 MAC programmable packet filtering is enabled, the RX/TX Number of Frames Removed Register increments with every frame removed in addition to the existing frames counted due to FIFO overflow ...
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... Behavior: The IXF1110 8B10B decoder substitutes a valid code word octet in its place. The packet transfer is aborted and marked as bad. The new internal length of the packet is equal to the byte position where the invalid symbol was. No packet fragments are seen at the next packet transfer. • ...
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... System Packet Interface Level 4 Phase 2 The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to a network processor or an ASIC. The interface implemented on the IXF1110 operates at data rates up to 12.8 Gbps and supports up to ten 1 Gbps MAC ports. The data path is 16 lanes wide in each direction, with each lane operating from 640 Mbps up to 800 Mbps. Port addressing, start/end packet control, and error control codes are all transferred “ ...
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... The gap between shorter packets is filled with idle control words. Note: Data packets with frame lengths less than 64 bytes should not be transferred to the IXF1110 MAC unless packet padding is enabled. If this rule is disregarded, unwanted fragments may be generated on the network at the SerDes interface ...
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... Arcs not annotated correspond to single cycles. In the IXF1110 MAC, the RX FIFO Status channel operates in a “pessimistic mode.” termed as pessimistic because it has the longest latency and largest impact on usable bandwidth. However DIP-2 check error is a rare event, there will be no ‘ ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Control Word Type. Set to either of the following values Idle or training control word 1 = Payload control word (payload transfer will immediately follow the control word) End-of-Packet (EOP) Status ...
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... The SPI4-2 specification allows the EOP Abort Payload Control word, which signals that the data associated with a particular frame is errored and should be dropped, or errored and dropped by the far-end link partner. In the IXF1110 MAC, all TX SPI4-2 transfers that end with an EOP Abort code have the TX SerDes CRC corrupted. This is true regardless of the MAC configuration. ...
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... Note: EOP Abort packets sent out on the RX SPI4-2 may have the packet size modified. When an EOP abort packet is received on the TX SPI4-2, the IXF1110 MAC sends the packet out to the SerDes interface with an invalid CRC and is recorded in the TX statistics as a CRC error. ...
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... Start-Up Parameters 5.2.2.1 CALENDAR_LEN CALENDAR_LEN specifies the length of each calendar sequence. As the IXF1110IXF1110 MAC is a 10-port device, CALENDAR_LEN is fixed at 10 for both TX and RX data paths. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
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... CALENDAR_M specifies the number of times the calendar port status sequence is repeated between the framing and DIP2 cycle of the calendar sequence. In the IXF1110 MAC, the TX path CALENDAR_M is fixed at 1; thus, the port status for ports will be transmitted only once between the framing and DIP2 cycle of the calendar sequence. ...
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... Since the required number of repeats is dependent on several characteristics of the system in which the IXF1110 MAC is being used, power on training (or training following loss of synchronization) will continue until synchronization is achieved and the calendar is provisioned. ...
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... During power-on training, an unlimited number of training cycles is sent by the data sourcing device. (The standard states that training must be sourced until a calendar has been provisioned.) In the IXF1110 MAC, the de-skew circuit waits until completion of its programmed average over the training patterns, ensuring that the required number of good DIP-4s is seen ...
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... The “1 1” framing pattern is not included in the parity calculation. The procedure described applies to either parity generation on the egress path or to check parity on the ingress path. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 68 SYNC 11 Port 0 Port 1 Enable ...
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... When a repeated “1 1” pattern is detected, all outstanding credits are cancelled and set to zero. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 0 1 Framing Pattern (not included 1 1 calculations) ...
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... HUNGRY and STARVING may only examine the most significant FIFO status bit. Note port is disabled on the IXF1110 MAC, FIFO status for the port is set to SATISFIED to avoid the possibility of any data being sent the controlling device. This applies to the IXF1110 MAC transmit path. ...
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... Any other control words in the middle will be seen as having a valid DIP-4 and will reset the Loss-of-Sync threshold counter back to zero. In order to avoid this, the IXF1110 MAC has altered the way in which the check is done for idle control words and training control words. We now only validate the first occurrence of the DIP-4 in both training control words and idle control words for correctness ...
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... Transmitter Operational Overview The transmit section of the IXF1110 has to serialize the Ten Bit Interface (TBI) data from the IXF1110 MAC section and outputs this data at 1.25 GHz differential signal levels. The 1.25 GHz differential SerDes signals are compliant with the Small Form Factor Pluggable (SFP) Multi- Source Agreement (MSA) ...
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... The static edge position is held at a constant position in the over-sampled by a constant adjustment of the sampling phases with the early and late signals. 5.3.3.4 Selective Power-Down The IXF1110 offers the ability to selectively power-down any of the SerDes ports that are not being used. This is done via page 176. 5.3.4 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 22. IXF1110-to-SFP Connections IXF1110 Pin Names TX_9:0_P TX_9:0_N RX_9:0_P RX_9:0_N 2 I C_CLK 2 I C_DATA_9:0 MOD_DEF_9:0 TX_DISABLE_9:0 TX_FAULT_9:0 RX_LOS_9:0 5.4.3 Functional Descriptions 5.4.3.1 High-Speed Serial Interface These signals are responsible for transfer of the actual data at 1.25 Gbps. The data is 8B/10B encoded and transmitted differentially at SerDes levels per the required specifications ...
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... TX_FAULT_9:0 These 10 pins are inputs to the IXF1110. These signals are pulled to a logic Low level by the optical module during normal operation, which indicates no fault condition exists fault is present, a logic High is received via the use of an external pull-up resistor at the IXF1110 pad. ...
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... The maximum clock rate of the interface is 100 kHz. All address select pins on the 2 internal E PROM are tied Low to give a device address equal to zero (00h). The specific interface in the IXF1110 supports only a subset of the full I features required to support the optical modules are implemented, leading to the following support features: 2 • ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 C interface is controlled through separate Prom family accesses to non-Atmel compatible devices will require to ...
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... The I C DATA_READ_FSM internal state machine takes over the task of transferring the actual data between the IXF1110 and the selected optical module (refer to the details in Section 5.4.4.2, “ The I C DATA_READ_FSM internal state machine places the received data into the ...
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... Specific protocol states are defined below, with an additional description of the hardware pins used on the interface. The Serial Clock Line (I clock and is driven off the rising edge by the IXF1110 and off the falling edge by the optical module. The IXF1110 has only one I 2 ...
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... Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8-bit words. The optical module E happens during the ninth clock cycle (see 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 80 DATA STABLE DATA CHANGE 2 2 ...
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... Write: Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller START 2 C_CLK is High 2 PROM returns to a standby state. 2 PROM, the device address or device ID is completely ...
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... IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller • The IXF1110 generates a start condition. • The IXF1110 sends a device address word with the Read/Write bit cleared to Low, signaling a Write operation. • The optical module acknowledges receipt of the device address word. • ...
Page 83
... LED DATA: This serial data is provided by the IXF1110 MAC to the external parallel-to-serial shift registers. • LED LATCH: This latch is provided by the IXF1110 MAC to latch the data on the parallel-to- serial shift registers. The LED_DATA stream provides data for 30 separate direct drive LEDs and allows three LEDs per MAC port. The three LED pins outlined above are detailed in Descriptions” ...
Page 84
... LED outputs. In this mode the LED DATA, LED CLK and LED LATCH signals are used. This mode is selected by setting bit 0 of the 5.5.3 LED Interface Signal Description The IXF1110 MAC LED interface consists of three output signal pins that are 2.5 V CMOS level pads. Table 23, “LED Signal Descriptions” descriptions. ...
Page 85
... LED_LATCH signal is active High during the Low period on the 36th LED_CLK cycle. This avoids any possibility of trying to latch data shifting through the register. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 86
... The power-on default for this register is 0x3FF, which means all ports are enabled. “Link LED Enable ($ by the system software. This enables the per-port link LEDs for the IXF1110 MAC. Link LEDs do not automatically update. For more details on which LEDs are affected by this register, refer to section Section 5.5.7.1, “ ...
Page 87
... LED Data Decodes Table 26 shows the data decode of the data for the IXF1110 MAC. 5.5.7.1 LED Signaling Behavior Table 26. LED Data Decodes MACPORT LED_DATA The operation in each mode for the decoded LED data in Datasheet ® ...
Page 88
... LEDs are not enabled, all of the LEDs will be off. 5.6 CPU Interface 5.6.1 General Description The CPU Interface block provides access to registers and statistics in the IXF1110 MAC. The interface is asynchronous externally and operates within the 125 MHz clock domain internally. The interface provides access to the following registers: • MAC Control • ...
Page 89
... MHz internally. In some applications, synchronous-to-asynchronous glue logic is required between the IXF1110 MAC and the system CPU. This glue logic must be designed so that the IXF1110 MAC Read and Write access times are not violated. It may be possible to interface without glue logic if the CPU can meet the timing seen in Figure 25, “ ...
Page 90
... CPU cycle to prevent erroneous Write operations to a register. UPX_WR_L This pin indicates there is data on the CPU data bus to be written to the IXF1110 MAC. A Low-to- High transition latches the data and a High-to-Low transition latches the address. This Write operation is active Low ...
Page 91
... Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The address to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]). 2. UPX_WR_L should be asserted by the CPU. The IXF1110 MAC latches the address. 3. The CPU drives valid data onto the processor bus (UPX_DATA[31:0]). ...
Page 92
... Pull-down through 10 K TDO Pull-up through TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to ensure reset of the TAP controller. For more information, refer to page 93 or the IEEE 1149 ...
Page 93
... Pull-up through 10 K TCK Pull-up through TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to ensure reset of the TAP controller. For more information, refer to page 93 or the IEEE 1149 ...
Page 94
... The bypass register is a one bit register that is used so the IXF110 can be bypassed to reduce the length of the JTAG chain when trying to access other devices on the chain besides the IXF1110 MAC. The BYPASS, HIGHZ, and CLAMP instructions connect this register between TDI and TDO ...
Page 95
... Maximum clock frequency of 100 kHz 5.8.5 LED Clock The IXF1110 MAC supportss a serial LED data stream. This interface implements a 2.5 V CMOS output clock with a maximum frequency of 720 Hz. The IXF1110 MAC supportss a serial LED data stream. The IXF1110 MAC meetss the following specifications for this clock: • ...
Page 96
... Follow the power-up and power-down sequence described in this section to ensure correct IXF1110 operation. The sequence covers all IXF1110 MAC digital and analog supplies. Caution: Failure to follow the power-up and power-down sequences will damage the IXF1110 MAC. 6.1.1 Power-Up Sequence Ensure that the 1.8 V supplies (VDD/AVDD1P8_1/AVDD1P8_2) are applied and stable prior to the application of the 2 ...
Page 97
... Table 32. Analog Power Balls Signal Name AVDD1P8_1 AVDD2P5_1 AVDD1P8_2 AVDD2P5_2 6.3 TX FIFO and RX FIFO Operation The IXF1110 MAC packet buffering is comprised of individual port FIFOs and system-interface FIFOs. Figure 28 illustrates the interaction of these FIFOs. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® ...
Page 98
... TX FIFO The IXF1110 MAC TX FIFOs are implemented with 4.5 KB for each port. This provides enough space for at least one maximum size packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate. ...
Page 99
... Failure to do this may result in packet loss. 6.3.1.3 TX FIFO Drain (IXF1110 Version) The IXF1110 can allow the SPI4-2 NPU or ASIC to dump data to the IXF1110 while the link is down. This allows the NPU or ASIC to empty its FIFOs, if necessary. The IXF1110 operates in the following manner under normal operating conditions: If the IXF1110 detects that the link is down for a given port, the SPI4-2 interface FIFO status bus indicates SATISFIED ...
Page 100
... The IXF1110 is ready to resume normal data transmission. 6.3.2 RX FIFO The IXF1110 MAC RX FIFOs are provisioned so that each port has its own 17.0 KB memory space. This is enough memory to ensure against an over-run on any port while transferring normal Ethernet frame-size data. The RX FIFOs are configured by default to automatically generate Pause control frames to initiate the following: • ...
Page 101
... DIP4 errors and data corruption. This will require a re-training once the TDCLK is stable. When the TDCLK is applied after the reset pin is released, a built-in feature in the IXF1110 MAC reactivates the internal reset once TDCLK is applied. The IXF1110 MAC extends this hardware reset internally to ensure synchronization of all internal blocks within the system ...
Page 102
... SerDes Power-Down Capabilities The IXF1110 has the ability to power down the TX and RX SerDes individually on each port (see Section 5.3, “SerDes Interface” on page power down the SerDes ports. Note: These sequences must be followed to ensure a port correctly operates when brought out of a power- down mode: 6 ...
Page 103
... The IXF1110 SerDes and Optical Module interfaces allow system designers to connect the IXF1110 to various optical transceivers. When using Small Form Factor Pluggable (SFP) optical transceivers to connect to the IXF1110, all SerDes and Optical Module status pins are used. Use Figure 29, “SFP-to-IXF1110 Connection” ...
Page 104
... VeeT 2 TxFault 3 TxDisable MOD_DEF 4 (2) MOD_DEF 5 (1) MOD_DEF 6 (0) 7 Rate Select NA 8 LOS 9 VeeR 10 VeeR 11 VeeR 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 104 VDD 3.3 V 4.7 k 4.7 k 4.7 k 4 TXFault 4 MOD_DEF(2) 5 MOD_DEF(1) 6 MOD_DEF(0) 8 LOS 3 TXDisable 18 TD+ 19 TD- 12 RD- 13 ...
Page 105
... Table 33. SFP-to-IXF1110 Connection (Sheet SFP SFP Pin Pin # Name 12 RD- 13 RD+ 14 VeeR 15 VccR 16 VccT 17 VeeT 18 TD+ 19 TD- 20 VeeT N/A N/A N/A N/A N/A N/A Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 106
... IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 7.0 Electrical Specifications Table 34 through Table 49 on page 122 represent the target specifications of the following IXF1110 MAC interfaces: • “CPU Timing Specification” • “JTAG Timing Specification” • “Transmit Pause Control Timing Specifications” ...
Page 107
... Operating Current Recommended Operating Temperature Recommended Storage Temperature Power Consumption 1. Typical values are at 25 testing. 2. Refer to the Intel® IXF1110 Thermal Design Guidelines (document number 250289). Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 108
... Differential Output Voltage Delta Differential Output Voltage (Complementary States) Offset (Common- Mode) Voltage Output Leakage Current 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 108 1 Symbol Min Typ Max V – – 0. 1.7 – ...
Page 109
... Exceeding these values will damage the device. Table 38. Undershoot/Overshoot Limits Ball Type 2.5 V CMOS 2.5 V LVTTL Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 38). Undershoot Overshoot -0.60 V 3.9 V -0.60 V 3.9 V Order Number: 250210, Revision: 009 07-Oct-2005 ...
Page 110
... Table 39. CPU Timing Parameters (Sheet Parameter UPX_ADD[12:0], UPX_CS_L Setup Time UPX_ADD[12:0], UPX_CS_L Hold Time UPX_RDY_L Assertion to UPX_RD_L De-assertion 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 110 T CAS T CDRS T CDRD T CAS T CWL ...
Page 111
... Read UPX_RDY_L de-assertion to UPX_WR_L Assertion Write UPX_RDY_L de-assertion to UPX_RD_L Assertion 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Symbol Min 24 T CRH (3x cycle CDRS T 8 ...
Page 112
... TCLK Low Time TCLK Falling Edge to TDO Valid TMS/TDI Setup to TCLK TMS/TDI Hold from TCLK 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 112 Tjc Tjl Tjh Tjval Tjsh Tjsu 1 Symbol Min Typ ...
Page 113
... Hold from TXPAUSEFR TXPAUSEFR Pulse to Pulse 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Tbtp Tpw Tsu Thd 1 Symbol Min Typ Max T 16 – ...
Page 114
... Table 42. Optical Module Interrupt Timing Parameters Parameter Change of state on MOD_DEF_9:0 or TX_FAULT_9:0 or RX_LOS_9:0 to assertion (active Low) on MOD_DEF_Int or TX_FAULT_Int or RX_LOS_Int 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 114 2 C Timing Specification Tdi 1 Symbol Min Typ T 24 – ...
Page 115
... Data In Hold Time Data In Setup time Inputs Rise Time 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller t HIGH LOW LOW t t HD.STA HD ...
Page 116
... C AC Timing Characteristics (Sheet Parameter Inputs Fall Time Stop Setup Time Data Out Hold Time Write Cycle Time 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 116 1 Symbol Min Typ t – – 4.7 – ...
Page 117
... Parameter Reset Pulse Width Reset Recovery Time 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Trw 1 Symbol Min Typ Max T 100 – – ...
Page 118
... LED_CLK Rising Edge to LED_LATCH Falling Edge LED_CLK Falling Edge to LED_LATCH Rising Edge 1. Typical values are at 25 testing. 2. Flash Rate = 100 ms, LED Mode 1. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 118 Tcyc Tlow Thi Tdatd 1 Symbol Min Typ Max T 1.36 – ...
Page 119
... Typical values are at 25 testing. NOTE: Refer to Table 21, “SerDes Driver TX Power Levels” on page 72 Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 39 illustrates the timing requirements for the IXF1110 Rt ...
Page 120
... Receive Eye Width Receiver termination impedance Signal detect level Total Receiver jitter tolerance 1. Typical values are at 25 testing. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 120 Normalized Power Symbol Min Typ Driver Setting – 1. – ...
Page 121
... TSCLK Rising Edge to TSTAT[1:0] Valid (Default operation) 1. Typical values are at 25 testing. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Td1 Td2 1 Symbol Min Typ T 1 – – ...
Page 122
... Typical values are at 25 testing. Table 50. SPI4-2 LVDS Rise/Fall Times Parameter Symbol Rise/Fall at RTsrc source Rise/Fall at sink RTsnk 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 122 Tsu1 Th1 Th2 Tsu2 1 Symbol Min Typ – ...
Page 123
... Register Definitions 8.1 Introduction This section provides information on the location and functionality of the IXF1110 MAC Control and Status Registers. 8.2 Document Structure This document is structured to give a general overview of the register map and an in-depth description of each bit of a register in later sections. 8.3 Graphical Representation Figure 42 represents an overview of the IXF1110 MAC Global Control Status Registers that are used to configure or report on all ports ...
Page 124
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 42. Memory Overview 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 124 Global Configuration -RX Block Configuration -TX Block Configuraiton Port 9 MAC Control & Statistics Port 8 MAC Control & Statistics Port 7 MAC Control & ...
Page 125
... The following section covers all of the registers that are replicated in each of the 10 ports in the IXF1110 MAC. These registers perform an identical function in each port. The address vector for the IXF1110 MAC is 11 bits wide. This allows for 7 bits of port-specific access and a 4-bit vector to address each port and all global registers. The address format is shown ...
Page 126
... RXFCSErrors RXTagged RXDataError Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 126 Register Bit Size MAC Control Registers (Port Index + Offset) Register Bit Size MAC RX Statistics Registers (Port Index + Offset) ...
Page 127
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size MAC RX Statistics Registers (Port Index + Offset) Register Bit Size MAC TX Statistics Registers (Port Index + Offset) ...
Page 128
... Fault Disable ($ 0x50B)” “JTAG ID Revision ($ 0x50C)” Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 128 Register Bit Size MAC TX Statistics Registers (Port Index + Offset) Register Bit Size ...
Page 129
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size RX Block Registers Order Number: 250210, Revision: 009 Ref 1 Mode ...
Page 130
... FIFO Info Out-of-Sequence ($ 0x621)” TX FIFO Number of Frames Removed on Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 130 Register Bit Size Order Number: 250210, Revision: 009 Ref ...
Page 131
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Register Bit Size Register Bit Size Register Order Number: 250210, Revision: 009 ...
Page 132
... C Control Ports 0-9 ($ 0x79B)” 2 “I C Data Ports 0-9 ($ 0x79C)” Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 132 Register Bit Size Order Number: 250210, Revision: 009 Ref 1 Mode Address ...
Page 133
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide details on the control and status registers associated Description Source MAC address bits 31-0. This address is inserted in the source address field when transmitting Pause frames, and is also used to compare against unicast Pause frames at the receiving side ...
Page 134
... Time Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 134 Description Contains the value of the lowest 32 bits of the destination address field transmitted in an internally generated flow control (pause) frame. Internally ...
Page 135
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved When a pause frame is sent, an internal timer checks when a new pause frame must be scheduled for transmission to keep the link partner in pause mode. ...
Page 136
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Table 71. RX Config Word ($ Port_Index + 0x16) (Sheet Bit Name Register Description: This register is used in the IXF1110 only for auto-negotiation. Register bits 15:0 are the “config_word” received from the link partner, as described in IEEE 802.3, Sub clause 37.2.1. 31:22 ...
Page 137
... Full Duplex 4:0 Reserved Read Only; CoR = Clear on Read Write; R/W = Read/Write Table 72. TX Config Word ($ Port_Index + 0x17) Bit Name Register Description: This register is used in the IXF1110 for auto-negotiation only. The contents of this register are sent as the config_word. 31:16 Reserved 15 NextPage 14 Reserved Remote Fault ...
Page 138
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 72. TX Config Word ($ Port_Index + 0x17) Bit Name 7 Sym Pause 6 Half Duplex 5 Full Duplex 4:0 Reserved Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. There is no way to automatically update the state of the Remote Fault bits for transmission. The state of these bits must be set by the system controller through the uP interface prior to enabling auto-negotiation. 3. Reserved bits must be written to ‘ ...
Page 139
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved This bit enables a Global filter on frames with a CRC Error. When CRCErrorPASS = 0, all frames with a CRC Error are marked as bad. ...
Page 140
... Port Multicast 15:0 Address High Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 140 Description This bit enables a Global filter on Broadcast frames. When B/CastDropEn = 0, all broadcast frames are 2 passed to the SPI4-2 Interface. ...
Page 141
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Counts the bytes received in all legal frames, including all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted ...
Page 142
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Table 77. MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet Name RxPkts65to127 Octets RxPkts128to255 Octets RxPkts256to511 Octets RxPkts512to1023 Octets RxPkts1024to1518 Octets RxPkts1519toMax Octets RxFCSErrors RxTagged RxDataError RxAlignErrors Read Only; CoR = Clear on Read Write; R/W = Read/Write 2 ...
Page 143
... The total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times. Note: RxRuntErrors is not supported in the IXF1110. Any runt or short packets received are not counted in this register. Note: The “ShortRuntsThreshold” Register controls the byte count used to determine the ...
Page 144
... SFD. This counter indicates fragment sizes illegal in all modes, and is only fully updated after reception of a good frame following a fragment. Note: RxShortErrors is not supported in the IXF1110. Any runt or short packets received are not counted in this register. Gigabit half-duplex event only Note: N/A - half-duplex only Records the number of sequencing errors that occur ...
Page 145
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Counts the bytes transmitted in all legal frames. The count includes all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted ...
Page 146
... TXTotalCollisions TXSingleCollisions Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 146 Description The total number of packets transmitted (including bad packets) that were [128-255] octets in length. Incremented for tagged packets with a ...
Page 147
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description A count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. A frame that is counted by an instance of this object is ...
Page 148
... TXFlowControlCollisions Send Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 148 Description Number of frames transmitted with a legal size, but with the wrong CRC field (also called FCS field) Number of pause MAC frames ...
Page 149
... Bit Name Register Description: A control register for each port in the IXF1110. Port ID = bit position in the register. To make a port active, the bit must be set High (for example, port 4 active implies register value = 0001.0000). Setting the bit to 0 disables the port. The default state for this register is for all 10 ports to be active ...
Page 150
... Register Description : A soft reset register for the core clock system (for example, the SYS125 clock). 31:1 Reserved Core Soft 0 Reset Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 150 Description Reserved Port 9 link link 1 = Link Port 8 link link 1 = Link Port 7 link ...
Page 151
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Table 83. CPU Interface ($ 0x508) Bit Name Register Description: CPU interface Endian select. This register allows the user to select the Endian of the CPU interface to allow various different CPUs to be connected to the IXF1110. 31:1 Reserved 0 Endian Read Only ...
Page 152
... Disable Port 7 LED Fault 6 Disable Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 152 Name Description Reserved 0 = Disable LEDs 1 = Enable LEDs 0 = Enable LED Mode 0 for use with SGS Thompson M5450 LED driver (Default) ...
Page 153
... JEDEC Cont. 7:1 JEDEC ID 0 Reserved Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. See the IXF1110 Specification Upate for the latest version. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ...
Page 154
... For all RX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:15 - Reserved and R. Bits 14:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 154 provide an overview of the RX Block Registers, which Description High watermark for RX FIFO port 0. The default value is 1856 bytes. When the amount of data ...
Page 155
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description High watermark for RX FIFO port 7. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC ...
Page 156
... Bits 31:15 - Reserved and R. Bits 14:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 156 Description Low watermark for RX FIFO port 5. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC ...
Page 157
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description This register counts all frames removed from the RX FIFO for port 0 by meeting one of the following conditions: • The RX FIFO on this port becomes full • ...
Page 158
... For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9): Bits 31:22 - Reserved and R. Bits 21:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 158 Description This register counts all frames removed from the RX FIFO for port 5 by meeting one of the following conditions: • ...
Page 159
... Reset Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Reserved Port De-assert reset 1 = Reset Port De-assert reset ...
Page 160
... Drop Enable Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 160 Description Reserved These bits are used in conjunction with the Packet Filter Control ($ Port_Index + 0x19)” allowing the user to select whether errored or filtered frames are to be dropped or not ...
Page 161
... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description These bits are used in conjunction with the Packet Filter Control ($ Port_Index + 0x19)” allowing the user to select whether errored or filtered frames are to be dropped or not ...
Page 162
... RX FIFO Overflow 0 Event Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 162 Description Port FIFO overflow event did not occur 1 = FIFO overflow event occurred Port FIFO overflow event did not occur ...
Page 163
... Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the TX Block Registers, which Order Number: 250210, Revision: 009 1 Address Type Default 0x600 ...
Page 164
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 164 Order Number: 250210, Revision: 009 1 Address Type Default ...
Page 165
... For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Order Number: 250210, Revision: 009 1 Address Type Default 0x60E R/W 0x000001D0 ...
Page 166
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. 07-Oct-2005 ® ...
Page 167
... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write 2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. Datasheet ® ...
Page 168
... For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. Table 97. TX FIFO Overflow Event ($ 0x61E) (Sheet ...
Page 169
... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Port FIFO overflow event did not occur 1 = FIFO overflow event occurred Port FIFO overflow event did not occur ...
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... TX FIFO Info 6 Out-of- Sequence Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 170 Description Port Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode Port Disable TX FIFO drain mode ...
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... R = Read Only; CoR = Clear on Read Write; R/W = Read/Write Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description Port FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred Port 4 ...
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... Removed on Port Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 172 Description This register counts the number of frames removed on port 6 due FIFO overflow. This register counts the number of frames removed on port 7 due FIFO overflow ...
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... This allows for a much larger DAT_MAX_T time-out period and provides a more than adequate granularity of selection. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the SPI4-2 Block Registers. ...
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... Reserved 3:0 Reserved Read Only; CoR = Clear on Read Write only; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 174 Description 00 = Normal mode not enter training based on a repeating “11” pattern on RSTAT[1: Train continuously 0 = The FIFO status is captured on the ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Description DIP4_Errors is the total number of DIP4 errors detected since this register was last read. DIP-4_Unlock is a SPI4-2 parameter specifying the number of incorrect DIP4 ...
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... Reserved 19:10 TPWRDWN[9:0] 9:0 RPWRDWN[9: Read Only; CoR = Clear on Read Write; R/W = Read/Write 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 176 Description Reserved Description Reserved Tx power-down for Ports 0 Power-down) Rx power-down for Ports 0 Power-down) Order Number: 250210, Revision: 009 ...
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... Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller provide an overview of the Optical Module Interface Block Registers. Description Reserved RX_LOS inputs for Ports 0-9 TX_FAULT inputs for Ports 0-9 MOD_DEF inputs for Ports 0-9 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 2 Table 110 Control Ports 0-9 ($ 0x79B) (Sheet Bit Name 26 no_ack-err CEnable Start 23 Reserved 22 Write Complete 21 Reserved 20 Read Valid Port Address 19:16 Select 3:0 15 Read/Write 14:11 Device ID Register 10:0 Address Read Only; CoR = Clear on Read Write only; R/W = Read/Write 2 Table 111 ...
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... Overall package dimensions Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 45, “552-Ceramic Ball Grid Array 181): Order Number: 250210, Revision: 009 07-Oct-2005 179 ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 9.2.1 Markings Figure 44 illustrates the IXF1110 MAC top label marking. In contrast to the Pb-Free (RoHS-compliant) package, the non-RoHS-compliant package does not have the “e1” symbol. Figure 44. Markings Topside fields not to scale Pin 1 mark Syww9001 9 ...
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... A01 Corner Note: All dimensions are in mm. Note: All dimensions are in mm. Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (575X) (ø ø (0.91 MAX) (I/O Pads) (0.33 MIN) (Reference) (23x) TYP 1 (23) (25 ± ...
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... Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Figure 46. CBGA Package Side View Diagram Note: All dimensions are in mm. 07-Oct-2005 ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 182 45L4867 (552) Solder ball C4 Encapsulant Fillet Chip 0.81 ± 0.1 (2 ...
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... Table 112. Product Ordering Information Number HFIXF1110CC B2 WFIXF1110CC B2 Figure 47. Ordering Information - Sample HF Datasheet ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Revision Ship Media RoHS-Compliant B2 Tray B2 Tray IXF 1110 C C ...