S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 93

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

Chip Select Inputs
The S1D15206 series can interface to microprocessor when CS1 is
LOW and CS2 is HIGH.
When these pins are set to any other combination, D0 to D7 are high
impedance. A0, RD, and WR input are disabled. However, the reset
signal is entered regardless of CS1 and CS2 setup. The internal IC
status including LCD driver circuit is held until a reset signal is
entered.
Access to Display Data RAM and Internal Registers
The S1D15206 series can perform a series of pipeline processing
between LSI’s using bus holder of internal data bus in order to match
the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data
•Write
•Read
Rev.3.5
MPU
Internal
MPU
Internal
timing
timing
D6(SCL)
WR
RD
DATA
Address
Read signal
Column
Bus holder
D7(S1)
WR
DATA
Bus holder
Write signal
address
CS1
CS2
A0
preset
Set address n
1
D7
N
n
2
Preset
Latched
D6
n
N
3
D5
N
Dummy read
4
EPSON
Figure 1
Figure 2
n+1
D4
N
5
D3
from display RAM in the first read (dummy) cycle, stores it in bus
holder, and outputs it onto system bus in the next data read cycle.
Also, the microprocessor temporarily stores display data in bus
holder, and stores it in display RAM until the next data write cycle
starts.
When viewed from the microprocessor, the S1D15206 series access
speed greatly depends on the cycle time rather than access time to the
display RAM (
from the microprocessor can increase. If the cycle time is inappro-
priate, the microprocessor can insert the NOP instruction that is
equivalent to the wait cycle setup. However, there is a restriction in
the display RAM read sequence. When an address is set, the
specified address data is NOT output at the immediately following
read instruction. The address data is output during second data read.
A single dummy read must be inserted after address setup and after
write cycle (refer to Figure 2).
n+1
Incremented
6
n
D2
N+1
Read address n
7
n+2
D1
t
n
ACC
8
and
n+2
D0
t
DS
n+1
9
). It shows the data transfer speed to/
D7
N+2
10
n+1
Read address n+1
n+3
D6
n:
N:
S1D15206 Series
11
Current data
Dummy data
n+3
D5
n+2
12
4–9