IDT72V2111 Integrated Device Technology, IDT72V2111 Datasheet - Page 8

• Manufacturer Part Number: IDT72V2111
• Description: 512k X 9 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

PROGRAMMING FLAG OFFSETS
72V2111 has internal registers for these offsets. Default settings are stated in the
footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The selection of the loading
method is done using the LD (Load) pin. During Master Reset, the state of the
LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on LD during Master Reset selects serial loading of offset
values and in addition, sets a default PAE offset value of 3FFH (a threshold 1,023
words from the empty boundary), and a default PAF offset value of 3FFH (a
threshold 1,023 words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition, sets a default PAE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
Full and Empty Flag offset values are user programmable. The IDT72V2101/
TM
262,144 x 9, 524,288 x 9
8
offset value of 07FH (a threshold 127 words from the empty boundary), and
a default PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
current offset values. It is only possible to read offset values via parallel read.
rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming
has been selected.
In addition to loading offset values into the FIFO, it also possible to read the
Figure 4, Programmable Flag Offset Programming Sequence, summa-
The offset registers may be programmed (and reprogrammed) any time
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