ATA5743 ATMEL Corporation, ATA5743 Datasheet - Page 14

• Manufacturer Part Number: ATA5743
• Description: Ata5743 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 6-3.
6.3.1
6.3.2
14
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
(Number of checked Bits: 3)
ATA5743
Bit-check Mode
Configuring the Bit Check
Timing Diagram for Complete Successful Bit Check
Start-up mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter, and signals due to noise. This is done by subsequent time
frame checks where the distances between two signal edges are continuously compared to a
programmable time window. The maximum count of this edge-to-edge test before the receiver
switches to receiving mode is also programmable.
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maxi-
mum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If N
set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if N
value. In polling mode, the bit-check time is not dependent on N
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
As demonstrated in
limits. If the edge-to-edge time t
bit-check limit, T
T
Figure 6-4.
For best noise immunity it is recommended to use a low span between T
This is achieved by using a fixed frequency at a 50% duty cycle for the transmitter preburst. For
this reason, a “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t
various edge-to-edge time periods, the bit-check limits must be programmed according to the
required span.
T
Lim_max
Start-up
, the bit check will be terminated and the receiver will switch to sleep mode.
Valid Time Window for Bit Check
Lim_max
Figure
1/2 Bit
Dem_out
, the check will be continued. If t
6-4, the time window for the bit check is defined by two separate time
1/2 Bit
Bit-check mode
ee
T
Bit-check
is between the lower bit-check limit, T
1/2 Bit
T
Lim_min
T
Lim_max
t
Bit check ok
ee
1/2 Bit
1/f
Sig
1/2 Bit
ee
ee
. Using preburst patterns that contain
is smaller than T
1/2 Bit
Bit-check
Receiving mode
Bit-check
.
Lim_min
Lim_min
Figure 6-3
Lim_min
is set to a lower
, and the upper
, or t
4839B–RKE–08/05
and T
Bit-check
ee
shows an
Bit-check
exceeds
Lim_max
in the
is
.