ATA5743 ATMEL Corporation, ATA5743 Datasheet - Page 21

• Manufacturer Part Number: ATA5743
• Description: Ata5743 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 6-16. Data Clock Disappears Because of a Logical Error
Figure 6-17. Output of the Data Clock After a Successful Bit Check
4839B–RKE–08/05
Dem_out
Data_out (DATA)
DATA_CLK
Dem_out
Data_out (DATA)
DATA_CLK
The delay of the data clock is calculated as follows:
t
t
depends on the capacitive load C
falling edge, t
Figure 6-19 on page 22
level of Data_Out, the data clock is issued after an additional delay t
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see section
Delay
Delay1
= t
is the delay between the internal signals Data_Out and Data_In. For the rising edge, t
Delay1
1
1
Receiving mode,
bit check active
Bit check ok
+ t
Delay1
1
1
Delay2
depends additionally on the external voltage V
Receiving mode,
data clock control
logic active
1
1
and
0
1
Figure 6-26 on page
L
1
1
at pin DATA and the external pull-up resistor R
Data
Start bit
Data
1
0
Logical error (Manchester code violation)
Receiving mode,
data clock control
logic active
?
1
29). When the level of Data_In is equal to the
0
1
Receiving mode,
bit check aktive
0
0
“Data Interface” on page
X
(see
1
1
Delay2
Figure 6-18 on page
.
0
0
ATA5743
pup
. For the
29).
Delay1
22,
21