ATA5743 ATMEL Corporation, ATA5743 Datasheet - Page 16

• Manufacturer Part Number: ATA5743
• Description: Ata5743 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 6-7.
6.3.3
6.3.4
6.3.5
16
Bit check
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Dem_out
Bit-check-
counter
ATA5743
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Start-up mode
T
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and T
Therefore, an average value for T
depends on the selected baud-rate range and on T
value for T
In the presence of a valid transmitter signal, T
nal, f
a longer period for T
If the bit check was successful for all bits specified by N
mode. As shown in
and the data clock is available after the start bit has been detected
connected microcontroller can be woken up by the negative edge at pin DATA or by the data
clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling
mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
converted into the output signal data. This processing depends on the selected baud-rate range
(BR_Range).
clock cycle T
after T
always an integral multiple of T
The minimum time period between two edges of the data signal is limited to t
Figure 6-9 on page
during data reception. At the same time, it limits the maximum frequency of edges at DATA. This
eases the interrupt handling of a connected microcontroller.
The maximum time period for DATA to stay Low is limited to T
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. T
data stream.
receiver has switched to receiving mode.
Start-up
0
Sig
XClk
, and the count of the checked bits, N
1
DATA_L_max
2 3 4 5 6
Bit-check
has elapsed. The edge-to-edge time period t
XClk
Figure 6-10 on page 17
Figure 6-8 on page 17
. This clock is also used for the bit-check counter. Data can change its state only
, resulting in lower current consumption in polling mode.
7
is thereby longer than the maximum time period indicated by the transmitter
Figure 6-3 on page
Bit-check
1
17). This implies an efficient suppression of spikes at the DATA output
2
3
4 5
, requiring a higher value for the transmitter preburst, T
Bit-check mode
T
6 7 8 9
Bit-check
XClk
.
10
Bit-check
illustrates how Dem_out is synchronized by the extended
1/2 Bit
shows an example where Dem_out remains Low after the
11 12
14, the internal data signal is then switched to pin DATA,
13 14 15 16 17 18 19
is given in the electrical characteristics. T
Bit-check
Bit-check
Lim_max)
. A higher value for N
Clk
. A higher baud-rate range causes a lower
is dependent on the frequency of that sig-
20
Bit check failed ( CV_Lim
Bit-check
21 22 23 24
ee
of the Data signal, as a result, is
, the receiver switches to receiving
Bit-check
DATA_L_max
(Figure 6-14 on page
Sleep mode
Bit-check
T
0
varies for each check.
Sleep
Lim_max )
ee
. This function is
thereby results in
Preburst
T
4839B–RKE–08/05
DATA_min
.
Bit-check
20). A
(see