WM8746 Wolfson Microelectronics plc, WM8746 Datasheet - Page 25

• Manufacturer Part Number: WM8746
• Description: 24-bit, 192khz 6-channel Dac With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8746
Table 13 Register Map Description
w
0000100
Attenuation
DACL1
0000101
Attenuation
DACR1
0000110
Attenuation
DACL2
0000111
Attenuation
DACR2
0001000
Master
Attenuation
(all channels)
0001001
Extended
interface
control
REGISTER
ADDRESS
BIT
7:0
7:0
7:0
7:0
7:0
8
8
8
8
8
0
1
MASTA[7:0]
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
R1A[7:0]
R2A[7:0]
L1A[7:0]
L2A[7:0]
LABEL
2SPD
ZCD
Not latched
Not latched
Not latched
Not latched
Not latched
11111111
11111111
11111111
11111111
11111111
DEFAULT
(0dB)
(0dB)
(0dB)
(0dB)
(0dB)
0
0
Attenuation level of left channel DACL1 in 0.5dB steps. See Table 8
Controls simultaneous update of all Attenuation Latches
Attenuation level of right channel DACR1 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation level of left channel DACL2 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation level of right channel DACR2 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for all channels in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Activates the split rate mode where the front channels run at 192kHz
and the rear four channels run at 96kHz.
Controls the operation of the zero crossing detect mechanism which
ensures that the volume is only updated on each channel when the
signal passes through midrail.
0: Store DACL1 in intermediate latch (no change to output)
1: Store DACL1 and update attenuation on all channels.
0: Store DACR1 in intermediate latch (no change to output)
1: Store DACR1 and update attenuation on all channels.
0: Store DACL2 in intermediate latch (no change to output)
1: Store DACL2 and update attenuation on all channels.
0: Store DACR2 in intermediate latch (no change to output)
1: Store DACR2 and update attenuation on all channels.
0: Store MASTA[7:0] in all intermediate latches (no change to
output)
1: Store DACR0 and update attenuation on all channels
0: Normal operation.
1: Split rate operation.
0: Enable zero detect.
1: Disable zero detect.
DESCRIPTION
PD, October 2008, Rev 4.2
Production Data
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