WM8766 Wolfson Microelectronics plc, WM8766 Datasheet - Page 12
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WM8766
Manufacturer Part Number
WM8766
Description
24-bit, 192khz 6-channel Dac
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8766.pdf
(36 pages)
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WM8766
DEVICE DESCRIPTION
INTRODUCTION
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AUDIO DATA SAMPLING RATES
WM8766 is a complete 6-channel DAC including digital interpolation and decimation filters and
switched capacitor multi-bit sigma delta DACs with digital volume controls on each channel and
output smoothing filters.
The device is implemented as 3 separate stereo DACs in a single package and controlled by a single
interface.
Each stereo DAC has its own data input DIN1/2/3. DAC word clock LRCLK, DAC bit clock BCLK and
DAC master clock MCLK are shared between them.
The Audio Interface may be configured to operate in either master or slave mode. In Slave mode,
LRCLK and BCLK are all inputs. In Master mode, LRCLK and BCLK are all outputs.
Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume
controls may be operated independently. In addition, a zero cross detect circuit is provided for each
DAC for the digital volume controls. The digital volume control detects a transition through the zero
point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values
change.
Control of internal functionality of the device is by 3-wire serial or pin programmable control interface.
The software control interface may be asynchronous to the audio data interface as control data will
be re-synchronised to the audio processing internally.
Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC.
In Slave mode selection between clock rates is automatically controlled. In master mode, the sample
rate is set by control bit DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are
allowed for the DAC, provided the appropriate master clock is input.
The audio data interface supports right justified, left justified and I
highly flexible DSP serial port interface.
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the DAC MCLK input
pin(s) with no software configuration necessary.
The DAC master clock for WM8766 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
In Slave mode the WM8766 has a master clock detection circuit that automatically determines the
relationship between the system clock frequency and the sampling rate (to within +/- 32 master
clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The WM8766
is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock
frequency inputs for the WM8766.
The signal processing for the WM8766 typically operates at an oversampling rate of 128fs. The
exception to this is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the
oversampling rate is 64fs.
2
S interface formats along with a
PD Rev 4.1 July 2005
Production Data
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