WM8740 Wolfson Microelectronics plc, WM8740 Datasheet - Page 16

• Manufacturer Part Number: WM8740
• Description: 24-bit, High Performance 192khz Stereo Dac
• Manufacturer: Wolfson Microelectronics plc

WM8740
REGISTER MAP
Table 5 Mapping of Program Registers
Table 6 Register Bit Descriptions
w
M0
M1
M2
M3
M4
REGISTER
0
1
2
3
4
B15
-
-
-
-
-
B14
-
-
-
-
-
BITS
[7:0]
[7:0]
[4:3]
[7:6]
[5:4]
8
8
0
1
2
0
1
2
3
4
8
6
B13
-
-
-
-
-
AR[7:0]
IW[1:0]
SF[1:0]
AL[7:0]
NAME
MUT
DEM
DIFF
CDD
LDR
OPE
ATC
REV
LRP
SR0
LDL
IZD
WM8740 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4
registers. Note that in hardware differential mode and 8X modes, software control is not available.
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.
I2S
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 7.
0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255
- ∞dB (mute),
B12
-
-
-
-
-
A2 (0) A1(0) A0(0)
A2(0) A1(0) A0(1)
A2(0) A1(1) A0(0)
A2(0) A1(1) A0(1)
A2(1) A1(1) A0(0)
B11
DEFAULT
FF
FF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B10
X = 0
DESCRIPTION
Attenuation data for left channel.
Attenuation data load control for left channel.
Attenuation data for right channel.
Attenuation data load control for right channel.
Left and right DACs soft mute control.
De-emphasis control.
Left and right DACs operation control.
Input audio data bit select.
Audio data format select.
Polarity of LRCIN select.
Attenuator control.
Digital filter slow roll-off select.
Output phase reverse.
Sampling rate select.
Infinite zero detection circuit control.
Differential output mode.
Clock loss detector disable.
B9
LDR
LDL
IZD
B8
-
-
AR7
SF1
AL7
B7
-
-
CDD DIFF1 DIFF0
AR6
AL6
SF0
B6
-
AR5
AL5
B5
-
-
REV
AR4
IW1
AL4
B4
AR3
SR0
AL3
IW0
B3
-
PD, Rev 4.3, August 2009
OPE
ATC
AR2
AL2
B2
-
Production Data
DEM
AR1
LRP
AL1
B1
-
MUT
AR0
AL0
I
B0
2
-
S
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