ADT7473 Analog Devices, Inc., ADT7473 Datasheet - Page 63

• Manufacturer Part Number: ADT7473
• Description: Dbcool Remote Thermal Monitor And Fan Controller
• Manufacturer: Analog Devices, Inc.

Table 24. Register 0x37—Dynamic
Bit
[2:0]
[5:3]
[7:6]
1
Table 25. Maximum PWM Duty Cycle
R
0x38
0x39
0x3A
1
2
3
This register becomes read-only when th
These registers set the maximum PWM duty cyc
These
If Bit 3
If Bit 3 of Configuration Register 4 (0x7D) is 0, then on a THERM overtemperature event, fans go to 100% PWM.
egister Address
registers become read-only when the Configuration Regis
of Configuration Register 4 (0x7D) is set, then on a THERM
Name
CYR1
CYL
CYR2
R/W
R/W
Bits
000
001
010
011
100
101
110
111
R/W
Bits
000
001
010
011
100
101
110
111
R/W
Bits
000
001
010
011
100
101
110
111
Description
3-bit remote 1 cycle value. The
the cont
thermal time constants that ne
Decreas
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
3-bit loca
adjustm
system h
control l
Decreas
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2 LSBs of 3-bit remote 2 cycle value
(Register 0x36). These three
loop for
constant
Decreas
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
102
4 cycle
R/W
R/W
R/W
R/W
ents in
oop.
rol loo
the Re
e Cycl
e Cycl
e Cycl
2
s that n
as ass
l tem
s (128 sec)
e Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this regis
T
perature cycl
e
ociated therm
e
e
p for the Remot
mote 2 chan
MIN
the control l
eed to be fo
le of t
Registers (Power-On Default = 0xFF)
Control Register 2 (Power-On Default = 0x00)
he PWM out
Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximu
Maximu
nel, in terms of number of mo
e value. These three bits define
oop for the local temperature c
bits define the delay time be
und to optimize the respons
al time constants that need to be
se three bits de
e 1 channel, in te
ed to be foun
ter 1 lock bit is set to 1. Any
overtemperature event, fans go to their maximum programmed PWM value as programmed here.
m duty cycle
m duty cycle for PWM
put.
. The MSB of the 3-bit c
Rev. A | Page 63 of 76
d
for PWM2 output, default = 100
fine the delay time between making s
to optimize the response of fans and
rms of number of monitoring cycles
3 output, default = 100% (0xFF).
subsequent attempts to wr
e of fans and the control loop.
tween making subsequent T
nitoring cycles. The system has associa
1, 2, 3
ode resides in Dynamic T
hannel, in terms of number of monit
the delay time between making subsequent T
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
10
20
Inc
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
24 cycles (128 sec)
48 cycles (256 sec)
found to optimize the response o
rease Cycle
1
% (0xFF).
ite to th
MIN
. The sy
the con
is register fail.
ubsequen
MIN
Contro
ter fail.
adjustm
stem has associated
trol loop.
l Re
t T
oring c
ted th
f fans
MIN
ents i
gister 1
adjustments in
and the
n the control
ermal time
ADT7473
ycles. The
MIN