ADT7473 Analog Devices, Inc., ADT7473 Datasheet - Page 64

• Manufacturer Part Number: ADT7473
• Description: Dbcool Remote Thermal Monitor And Fan Controller
• Manufacturer: Analog Devices, Inc.

ADT7473
Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x01)
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Table 27. Register 0x41—Inte upt Status Reg
Bit
[1]
[2]
[4]
[5]
[6]
[7]
Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Name
RIT
LT
R2T
OOL
V
V
Name
STRT
LOCK
RDY
FSPD
VxI
FSPDIS
TODIS
RES
Name
OVT
FAN1
FAN2
FAN3
F4P
D1
D2
CCP
CC
R/W
Re
Re
Read only
R
Read only
Read
R/W
Read only
Read only
Read only
Read only
Read only
R/W
Read only
Read only
Read only
ead only
R/W
R/W
Write once
Read only
R/W
R/W
R/W
R/W
ad only
ad only
only
Description
V
re ster only if the
V
only if the error condition ha
R1T = 1 indicates the R
the status register
LT 1 indicates the
status register only
R2T = 1 indicates the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if
OOL = 1 indicates an out-of-
logical OR of a
whether any o
out-of-limit, w
Description
OVT = 1 indicates one of the THERM overtemperature limits is exceeded. This bit is cleared on a read of the
status register when the temperature drops below THERM – T
FAN1 = 1 indicates Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the
PWM1 output is off.
FAN2 = 1 indicates Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the
PWM2 output is off.
FAN3 = 1 indicates Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
F4P = 1 indicates Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3
output is off.
When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO.
If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM timer limit register (Reg. 0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
C
C
Description
Logic
Logic 0 disables m
This bit is not loc
Logic 1 locks all l
only and cannot
rogue programs,
This bit is set t
system monitor g.
W
re
BIOS should set
co
usage
Lo
timeout selected.
When
SMBu
Reserved.
gi
rr
CP
C
=
= 1 ind
gisters (0x30 to
hen set to 1, th
ntroller and to
gic 1 disables f
= 1 indicates th
s controller
1 enables m
. (This is a lo
this bit is s
icates th
ll status bits in
f the voltage, temperature, or fan sp
hich saves the need to read Interrupt Status
o 1
in
this bit to a 1 when the ADT7473 is configured to measure current from an ADI ADOPT
imit values to their current settings. Once this bit is set, all lockable registers become read-
only if the error condition has subsided.
ked when Bit 1 (LOCK bit) has been written. This bit remains writable after lock bit is se
be modified until the ADT7473 is powered down and powered up again. This prevents
is bit runs all fans at maxi
et to 1, the SMBus timeout feature is enabled. This allows the ADT7473 to be used with
error condition has subsided.
an spin-up for t
s that cannot handle SMBus timeouts. (This is a lockable bit.)
such as viruses, from modifying critical system l
e V
measure the C
by the ADT7473 to indicate only
if the erro
0x32). Power-o
ister 1 (Power-On Default = 0x00)
onitoring and PWM control outputs based on the limit settings programmed.
ckable bit.)
e V
local low or high temperature has been exceeded. This bit is cleared on a read of the
onitoring and PWM control based on the default power-up limit settings.
CC
CCP
emote 1 low or high temperature has been exceeded. This bit is cleared on a r
high or low limit has been e
the error condition has subsided.
high or low limit has been exceeded. This bit is cleared on a read of the
limit event has been latched in Interrupt Status Reg
s subsided.
I
r condition has subsided.
nterrupt Status Reg
Rev. A | Page 64 of 76
PU’s core voltage. This bit allows monitoring software to display CPU watts
wo TACH pulses. Instead, the PWM outputs go high for the entire fan spin-up
n default = 0. This bit is not locked at any time.
mum speed as programmed in th
ister 2. Software can test this b
eed readings represented by
xceeded. This bit is cleared on a read of the status register
that the device is fully po
Register 2 every inter
HYST
.
imit settings. (This is a lockable bit.)
wer
e maximum PWM dut
ister 2 (0x42). This bi
Interrupt Sta
it in isolation to dete
rupt o
ed up and ready to begin
r polling cycle.
tus Register 2 are
status
y cycle
t is a
ead of
rmine
®
t.
VRM