ADT7460 Analog Devices, Inc., ADT7460 Datasheet - Page 38

• Manufacturer Part Number: ADT7460
• Description: Dbcool? Remote Thermal Controller And Fan Controller
• Manufacturer: Analog Devices, Inc.

ADT7460
Table 48. Register 0x37—Dynamic T
Bit
<2:0>
<5:3>
<7:6>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no
effect.
Nam
CY
CYL
C
YR2
R1
e
R
Read/W ite
Read/W ite
Read/W te
/W
r
r
ri
Descr
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subse
adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles.
The system has associated thermal time constants that need to be found to optimize the response
fans and the control loop.
Bits
000
001
010
011
100
101
110
111
3-Bit Local Temperature Cycle Value. These three bits define the delay time between making
subsequent T
of monitoring cycles. The system has associated thermal time con
optimize the response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic TMIN Control
Register 1 (Reg. 0x36). These three bits def
adjustments in th
The system has associated thermal time constants that need to be found to optimize the response
fans and the control loop.
Bits
000
001
010
011
100
101
110
111
MIN
Control Register 2 (Power-On Default =
iption
MIN
adjustments in the control loop for l
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
e control loop for the Remote 2 channel, in terms of number of monitoring cycles.
Rev. C | Page 38 of 52
ine the delay time between making subsequent T
Increase Cycle
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
Increase Cycle
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
Increase Cycle
8 Cy
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles
512 Cycles (64 s)
1024 Cycles (128 s)
0x00)
cles (1 s)
ocal temperature channel, in terms of number
(32 s)
stants that need to be found to
quent T
MIN
MIN
of
of