AMIS-30624 AMI Semiconductor, Inc., AMIS-30624 Datasheet - Page 42

• Manufacturer Part Number: AMIS-30624
• Description: I2c Microstepping Motordriver
• Manufacturer: AMI Semiconductor, Inc.

AMIS-30624 I
16.5.2. Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Figure 28). Of course, set-up and hold times
must also taken into account (see Table 6). When AMIS-30624 doesn’t acknowledge the slave address, the data line will be left HIGH.
The master can than generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If AMIS-30624 as slave-receiver does acknowledge the slave address but later in the transfer cannot receive any more data bytes, this
is indicated by generating a not-acknowledge on the first byte to follow. The master generates than a STOP or a repeated START
condition.
If a master-receiver is involved in the transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge
on the last byte that was clocked out of the slave. AMIS-30624 as slave-transmitter shall release the data line to allow the master to
generate STOP or repeated START condition.
16.5.3. Clock Generation
The master generates the clock on the SCK line to transfer messages on the I
clock.
16.6 Data Formats with 7-bit Addresses
Data transfers follow the format shown in Figure 29. After the START condition (S), a slave address is sent. This address is 7-bit long
followed by an eighth bit which is a data direction bit (R/W) – a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for
data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it can generate a repeated START (Sr) and address another slave without
first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
AMI Semiconductor – Apr. 2007, Rev 3.1, M-20664-003
www.amis.com
SCK
SDA
START
condition
START
ADDRESS
1 - 7
2
C Microstepping Motordriver
SDA by master
SDA by slave
transmitter
receiver
SCK from
master
R/W
8
condition
START
START
ACK
9
Figure 28: Acknowledge on the I
Figure 29: A Complete Data Transfer
MSB
1
Master releases the Data line
1 - 7
DATA
2
42
Not acknowledged
Acknowledged
clock puse from master
Aknowledge related
8
2
8
C-bus
2
C-bus. Data is only valid during the HIGH period of the
ACK
9
9
Slave pulls data line
low if Acknowledged
1 - 7
DATA
PC20070217.5
PC20070217.6
8
ACK
9
Data Sheet
condition
STOP
STOP