PIC16F616 Microchip Technology Inc., PIC16F616 Datasheet - Page 117

• Manufacturer Part Number: PIC16F616
• Description: 14-pin Flash-based, 8-bit Cmos Microcontrollers
• Manufacturer: Microchip Technology Inc.

12.4
The
sources of interrupt:
• External Interrupt RA2/INT
• Timer0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt (PIC16F616/16HV616 only)
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt (PIC16F616/16HV616 only)
• Enhanced CCP Interrupt (PIC16F616/16HV616
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Enhanced CCP Interrupt
© 2007 Microchip Technology Inc.
only)
PIC16F610/616/16HV610/616
Interrupts
has
PIC16F610/616/16HV610/616
multiple
Preliminary
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For
comparators, ADC, Enhanced CCP modules, refer to
the respective peripheral section.
12.4.1
The external interrupt on the RA2/INT pin is edge-
triggered; either on the rising edge if the INTEDG bit of
the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
RA2/INT pin, the INTF bit of the INTCON register is set.
This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 12-9 for timing of wake-up from Sleep through
RA2/INT interrupt.
Note:
Note 1: Individual interrupt flag bits are set,
additional
2: When an instruction that clears the GIE
RA2/INT INTERRUPT
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
information
of
the
on
DS41288C-page 115
status
Timer1,
of
Timer2,
their